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1. general description the lpc3220/30/40/50 embedded microcontrollers were designed for low power, high performance applications. nxp achieved t heir performance goals using a 90 nanometer process to implement an arm926ej-s cpu core with a vector floating point co-processor and a large set of standard peripherals including usb on-the-go. the lpc3220/30/40/50 operates at cpu frequencies of up to 266 mhz. the nxp implementation uses a arm926ej-s cpu core with a harvard architecture, 5-stage pipeline, and an integral memory management unit (mmu). the mmu provides the virtual memory ca pabilities needed to support the multi-programmin g demands of modern operating systems. the arm926ej-s also has a hardware based set of dsp instruction extensions, which includes single cycle mac operations, and hardware based native jazelle java byte-code execution. the nxp implementation has a 32 kb instruction cache and a 32 kb data cache. for low power consumption, the lpc3220/30/ 40/50 takes advantage of nxp?s advanced technology development to optimize intrinsic power and uses software controlled architectural enhancements to optimize application based power management. the lpc3220/30/40/50 also includes 256 kb of on-chip static ram, a nand flash interface, an ethernet mac, an lcd controlle r that supports stn and tft panels, and an external bus interface that supports sdr and ddr sdram as well as static devices. in addition, the lpc3220/30/40/50 includes a u sb 2.0 full-speed interface, seven uarts, two i 2 c-bus interfaces, two spi/ssp ports, two i 2 s-bus interfaces, two single output pwms, a motor control pwm, six general purp ose timers with capture inputs and compare outputs, a secure digital (sd) interface, and a 10-bit analog-to-digital converter (adc) with a touch screen sense option. for additional documentation, see section 15 ? references ? . 2. features and benefits ? arm926ej-s processor, running at cpu clock speeds up to 266 mhz. ? vector floating point (vfp) coprocessor. ? 32 kb instruction cache and 32 kb data cache. ? up to 256 kb of internal sram (iram). ? selectable boot-up from various external devices: nand flash, spi memory, usb, uart, or static memory. lpc3220/30/40/50 16/32-bit arm microcontrollers; hardware floating-point coprocessor, usb on-the-go, and emc memory interface rev. 2.1 ? 24 june 2014 product data sheet
lpc3220_30_40_50 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 2.1 ? 24 june 2014 2 of 80 nxp semiconductors lpc3220/30/40/50 16/32-bit arm microcontrollers ? multi-layer ahb system that provides a se parate bus for each ahb master, including both an instruction and data bus for the cpu, two data busses for the dma controller, and another bus for the usb controller, one for the lcd, and a final one for the ethernet mac. there are no arbitration de lays in the system unless two masters attempt to access the same slave at the same time. ? external memory controller for ddr and sd r sdram as well as for static devices. ? two nand flash controllers: one for single-level nand flash devices and the other for multi-level nand flash devices. ? master interrupt controller (mic) and two slav e interrupt controllers (sic), supporting 74 interrup t sources. ? eight channel general purpose dma (gpdma) controller on the ahb that can be used with the sd card port, the high-speed uarts, i 2 s-bus interfaces, and spi interfaces, as well as memory-to-memory transfers. ? serial interfaces: ? 10/100 ethernet mac with dedicated dma controller. ? usb interface supporting either device, host (ohci compliant), or on-the-go (otg) with an integral dma controller and dedicated pll to generate the required 48 mhz usb clock. ? four standard uarts with fractional baud rate generation and 64 byte fifos. one of the standard uarts supports irda. ? three additional high-speed uarts intend ed for on-board communications that support baud rates up to 921 600 when using a 13 mhz main oscillator. all high-speed uarts provide 64 byte fifos. ? two spi controllers. ? two ssp controllers. ? two i 2 c-bus interfaces with standard open-drain pins. the i 2 c-bus interfaces support single master, slave, and multi-master i 2 c-bus configurations. ? two i 2 s-bus interfaces, each with separate input and output channels. each channel can be operated independently on three pins, or both input and output channels can be used with only four pins and a shared clock. ? additional peripherals: ? lcd controller supporting both stn and tft panels, with dedicated dma controller. programmable display resolution up to 1024 ? 768. ? secure digital (sd) memory card interface, which conforms to the sd memory card specification version 1.01 . ? general purpose (gp) input, output, and i/o pins. includes 12 gp input pins, 24 gp output pins, and 51 gp i/o pins. ? 10-bit, 400 khz analog-to-digital converter (adc) with input multiplexing from three pins. optionally, the adc can operate as a touch screen controller. ? real-time clock (rtc) with separate power pin and dedicated 32 khz oscillator. nxp implemented the rtc in an independent on-chip power domain so it can remain active while the rest of the chip is not powered. the rtc also includes a 32-byte scratch pad memory. ? 32-bit general purpose high-speed timer with a 16-bit pre-scaler. this timer includes one external capture input pin a nd a capture connection to the rtc clock. interrupts may be generated using three match registers.
lpc3220_30_40_50 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 2.1 ? 24 june 2014 3 of 80 nxp semiconductors lpc3220/30/40/50 16/32-bit arm microcontrollers ? six enhanced timer/counters which are ar chitecturally identical except for the peripheral base address. two capture inputs and two match outputs are pinned out to four timers. timer 1 brings out a third match output, timers 2 and 3 bring out all four match outputs, timer 4 has one match output, and timer 5 has no inputs or outputs. ? 32-bit millisecond timer driven from th e rtc clock. this timer can generate interrupts using two match registers. ? watchdog timer clocked by the peripheral clock. ? two single-output pwm blocks. ? motor control pwm. ? keyboard scanner function allows automatic scanning of an up to 8 ? 8 key matrix. ? up to 18 external interrupts. ? standard arm test/debug interface for compatibility with existing tools. ? emulation trace buffer (etb) with 2048 ? 24 bit ram allows trace via jtag. ? stop mode saves power while allowing many peripheral functions to restart cpu activity. ? on-chip crystal oscillator. ? an on-chip pll allows cpu operation up to the maximum cpu rate without the requirement for a high frequency crystal. another pll allows operation from the 32 khz rtc clock rather than the external crystal. ? boundary scan for simplified board testing. ? user-accessible unique serial id number for each chip. ? tfbga296 package with a 15 mm ? 15 mm ? 0.7 mm body. 3. applications ? consumer ? medical ? industrial ? network control
lpc3220_30_40_50 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 2.1 ? 24 june 2014 4 of 80 nxp semiconductors lpc3220/30/40/50 16/32-bit arm microcontrollers 4. ordering information [1] f = ?40 ? c to +85 ? c temperature range. note that revision ?a? parts with and without the /01 suffix are identical. for example, lpc3220fet296 revision ?a? is identica l to lpc3220fet296/01 revision ?a?. [2] available starting with revision ?a?. 4.1 ordering options table 1. ordering information type number [1] package name description version lpc3220fet296/01 [2] tfbga296 plastic thin fine-pitch ball grid array package; 296 balls sot1048-1 lpc3230fet296/01 [2] tfbga296 plastic thin fine-pitch ball gr id array package; 296 balls sot1048-1 lpc3240fet296/01 [2] tfbga296 plastic thin fine-pitch ball grid array package; 296 balls sot1048-1 lpc3250fet296/01 [2] tfbga296 plastic thin fine-pitch ball grid array package; 296 balls sot1048-1 table 2. part options type number sram (kb) 10/100 ethernet lcd controller temperature range ( ?c) package lpc3220fet296/01 128 0 0 ? 40 to +85 tfbga296 lpc3230fet296/01 256 0 1 ? 40 to +85 tfbga296 lpc3240fet296/01 256 1 0 ? 40 to +85 tfbga296 lpc3250fet296/01 256 1 1 ? 40 to +85 tfbga296
lpc3220_30_40_50 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 2.1 ? 24 june 2014 5 of 80 nxp semiconductors lpc3220/30/40/50 16/32-bit arm microcontrollers 5. block diagram fig 1. block diagram of lpc3220/30/40/50 arm 9ejs d-cache 32 kb i-cache 32 kb data instruction ethernet phy interface usb transceiver interface lcd panel interface external memory controller rom 16 kb sram 256 kb usb dma etb sdram standard uart 4 i2c 2 timers 6 watchdog timer debug system control hs uart 3 key scanner 10-bit adc/ts uart control rtc pwm 2 gpio m1m0 ahb to apb bridge ahb to apb bridge ahb to apb bridge master layer 0123456 slave port 0 1 7 6 5 3 2 = master/slave connection supported by the multilayer ahb matrix 32-bit ahb matrix apb slaves fab slaves ahb slaves apb slaves port 3 port 4 port 0 32-bit wide external memory etb etm 9 vfp9 lcd ethernet motor control pwm 002aae397 mmu d-side controller i-side controller dma controller ethernet 10/100 mac usb otg controller lcd controller mlc nand slc nand sd card spi 2 i2s 2 ssp 2 interrupt control register interfaces
lpc3220_30_40_50 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 2.1 ? 24 june 2014 6 of 80 nxp semiconductors lpc3220/30/40/50 16/32-bit arm microcontrollers 6. pinning information 6.1 pinning fig 2. pin configuration for sot1048-1 (tfbga296) 002aae398 transparent top view v u t r p n l j m k h g f e d b c a 24681012 13 14 15 17 16 18 1357911 ball a1 index area table 3. pin allocati on table (tfbga296) pin symbol pin symbol pin symbol row a a3 i2c2_scl a4 i2s1tx_clk/mat3[0] a5 i2c1_scl a6 ms_bs/mat2[1] a7 ms_dio1/mat0[1] a8 ms_dio0/mat0[0] a9 spi2_datio/mosi1/lcdvd[20] [1] a10 spi2_datin/miso1/ lcdvd[21] [1] /gpi_27 a11 gpio_1 a12 gpio_0 a13 gpo_21/u4_tx/lcdvd[3] [1] a14 gpo_15/mcoa1/lcdfp [1] a15 gpo_7/lcdvd[2] [1] a16 gpo_6/lcdvd[18] [1] row b b2 gpo_20 b3 gpo_5 b4 i2s1tx_ws/cap3[0] b5 p0[ 0]/i2s1rx_clk b6 i2c1_sda b7 ms_sclk/mat2[0] b8 ms_dio2/mat0[2] b9 spi1_datio/mosi0/mci2 b10 spi2_clk/sck1/lcdvd[23] [1] b11 gpio_4/ssel1/lcdvd[22] [1] b12 gpo_12/mcoa2/lcdle [1] b13 gpo_13/mcob1/lcddclk [1] b14 gpo_2/mat1[0]/lcdvd[0] [1] b15 gpi_19/u4_rx b16 gpi_8/key_col6/ spi2_busy/enet_rx_dv [2] b17 n.c. row c c1 flash_rd c2 gpo_19 c3 gpo_0/tst_clk1 c4 usb_atx_int c5 usb_se0_vm/u5_tx c6 tst_clk2 c7 gpi_6/hstim_cap/ enet_rxd2 [2] c8 ms_dio3/mat0[3] c9 spi1_clk/sck0
lpc3220_30_40_50 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 2.1 ? 24 june 2014 7 of 80 nxp semiconductors lpc3220/30/40/50 16/32-bit arm microcontrollers c10 spi1_datin/miso0/gpi_25/ mci1 c11 gpio_3/key_row7/ enet_mdio [2] c12 gpo_9/lcdvd[9] [1] c13 gpo_8/lcdvd[8] [1] c14 gpi_2/cap2[0]/ enet_rxd3 [2] c15 gpi_1/service c16 gpi_0/i2s1r x_sda c17 key_row4/enet_txd0 [2] c18 key_row5/enet_txd1 [2] row d d1 flash_rdy d2 flash_ale d3 gpo_14 d4 gpo_1 d5 usb_dat_vp/u5_rx d6 usb_oe_tp d7 p0[1]/i2s1rx_ws d8 gpo_4 d 9 gpio_2/key_ro w6/enet_mdc [2] d10 gpo_16/mcob0/lcdenab [1] / lcdm [1] d11 gpo_18/mcoa0/lcdlp [1] d12 gpo_3/lcdvd[1] [1] d13 gpi_7/cap4[0]/mcabort d14 pwm_out1/lcdvd[16] [1] d15 pwm_out2/intstat/lcdvd[19] [1] d16 key_row3/enet_tx_en [2] d17 key_col2/enet_rx_er [2] d18 key_col3/enet_crs [2] row e e1 flash_io[3] e2 flash_io[7] e3 flash_ce e4 i2c2_sda e5 usb_i2c_scl e6 usb_i2c_sda e7 i2s1tx_sda/mat3[1] e8 gp o_11 e9 gpio_5/ssel0/mci0 e10 gpo_22/u7_hrts/ lcdvd[14] [1] e11 gpo_10/mcob2/lcdpwr [1] e12 gpi_9/key_col7/enet_col [2] e13 gpi_4/spi1_busy e14 key_row1/enet_txd2 [2] e15 key_row0/enet_tx_er [2] e16 key_col1/enet_rx_clk [2] / enet_ref_clk [2] e17 u7_rx/cap0[0]/ lcdvd[10] [1] /gpi_23 e18 u7_tx/mat1[1]/lcdvd[11] [1] row f f1 flash_io[2] f2 flash_wr f3 flash_cle f4 gpi_3 f5 vss_ioc f6 vss_iob f7 vdd_ioc f8 vdd_iob f9 vdd_iod f10 vss_iod f11 vss_iod f12 vss_iod f13 vdd_iod f14 key_row2/enet_txd3 [2] f15 key_col0/enet_tx_clk [2] f16 key_col5/enet_rxd1 [2] f17 u6_irrx/gpi_21 f18 u5_rx/gpi_20 row g g1 emc_dycs1 g2 flash_io[5] g3 flash_io[6] g4 resout g5 vss_ioc g6 vdd_ioc g7 vdd_core g8 vss_core g9 vdd_core g10 vss_core g11 vdd_core g12 vss_core g13 u7_hcts/cap0[1]/ lcdclkin [1] /gpi_22 g14 dbgen g15 key_col4/enet_rxd0 [2] g16 u6_irtx g17 sysclken/lcdvd[15] [1] g18 jtag_tms row h h1 emc_oe h2 flash_io[0] h3 flash_io[1] h4 flash_io[4] h5 vss_ioc h6 vdd_ioc h7 vss_core h12 vss_iod h13 vdd_ioa h14 jtag_tck h15 u5_tx table 3. pin allocati on table (tfbga296) pin symbol pin symbol pin symbol
lpc3220_30_40_50 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 2.1 ? 24 june 2014 8 of 80 nxp semiconductors lpc3220/30/40/50 16/32-bit arm microcontrollers h16 highcore/lcdvd[17] [1] h17 jtag_ntrst h18 jtag_rtck row j j1 emc_a[20]/p1[20] j2 emc_a[ 21]/p1[21] j3 emc_a[22]/p1[22] j4 emc_a[23]/p1[23] j5 vdd_ioc j6 vdd_emc j7 vdd_core j12 vdd_core j13 vdd_ioa j14 u3_rx /gpi_18 j15 jtag_tdo j16 jtag_tdi j17 u3_tx j18 u2_hcts/u3_cts/gpi_16 row k k1 emc_a[19]/p1[19] k2 emc_a[ 18]/p1[18] k3 emc_a[16]/p1[16] k4 emc_a[17]/p1[17] k5 vss_emc k6 vdd_emc k7 vdd_emc k12 vss_core k13 vss_ioa k14 vdd_rtc k15 u1_rx/cap1[0]/gpi_15 k16 u1_tx k17 u2_tx/u3_dt r k18 u2_rx/u3_dsr/gpi_17 row l l1 emc_a[15]/p1[15] l2 emc_cke1 l3 emc_a[0]/p1[0] l4 emc_a[1]/p1[1] l5 vss_emc l6 vdd_emc l7 vss_core l12 vdd_corefxd l13 vdd_rtccore l14 vss_rtccore l15 p0[4]/i2s0rx_ws/lcdvd[6] [1] l16 p0[5]/i2s0tx_sda/lcdvd[7] [1] l17 p0[6]/i2s0tx_clk/ lcdvd[12] [1] l18 p0[7]/i2s0tx_ws/lcdvd[13] [1] row m m1 emc_a[2]/p1[2] m2 emc_a[ 3]/p1[3] m3 emc_a[4]/p1[4] m4 emc_a[8]/p1[8] m5 vss_emc m6 vdd_emc m7 vdd_core m8 vdd_emc m9 vss_core m10 vss_core m11 vdd_core m12 vss_core m13 vdd_corefxd m14 reset m15 onsw m16 gpo_23/u2_hrts/u3_r ts m17 p0[2]/i2s0rx_sda/ lcdvd[4] [1] m18 p0[3]/i2s0rx_clk/lcdvd[5] [1] row n n1 emc_a[5]/p1[5] n2 emc_a[ 6]/p1[6] n3 emc_a[7/p1[7] n4 emc_a[12]/p1[12] n5 vss_emc n6 vss_emc n7 vdd_emc n8 vdd_emc n9 vdd_emc n10 vdd_emc n11 vdd_emc n12 vdd_ad n13 vdd_ad n14 vdd_fuse n15 vdd_rtcosc n16 gpi_5/u3_dcd n17 gpi_28/u3_ri n18 gpo_17 row p p1 emc_a[9]/p1[9] p2 emc_a[10 ]/p1[10] p3 emc_a[11]/p1[11] p4 emc_dqm[1] p5 emc_dqm[3] p6 vss_emc table 3. pin allocati on table (tfbga296) pin symbol pin symbol pin symbol
lpc3220_30_40_50 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 2.1 ? 24 june 2014 9 of 80 nxp semiconductors lpc3220/30/40/50 16/32-bit arm microcontrollers [1] lcd on lpc3230 and lpc3250 only. [2] ethernet on lpc3240 and lpc3250 only. p7 vss_emc p8 vss_emc p9 vss_emc p10 vss_emc p11 vss_emc p12 emc_bls[3] p13 vss_ad p14 vss_osc p15 vdd_pllusb p16 rtcx_in p17 rtcx_ out p18 vss_rtcosc row r r1 emc_a[13]/p1[13] r2 emc_ a[14]/p1[14] r3 emc_dqm[0] r4 emc_wr r5 emc_cas r6 emc_dycs0 r7 emc_d[1] r8 emc_d[7] r9 emc_d[17]/emc_dqs1 r10 emc_d[24]/p2[5] r11 emc_cs1 r12 emc_bls[2] r13 ts_xp r14 pll397_loop r15 sysx_out r16 vss_pllusb r17 vdd_pllhclk r18 vss_pllhclk row t t1 emc_dqm[2] t2 emc_ras t3 emc_clk t4 emc_clkin t5 emc_d[2] t6 emc_d[6] t7 emc_d[11] t8 emc_d[14] t9 emc_d[20]/p2[1] t10 emc_d[23]/p2[4] t11 emc_d[27]/p2[8] t12 emc_cs2 t13 emc_bls[1] t14 adin1/ts_xm t15 vss_pll397 t16 vdd_pll397 t17 sysx_in t18 vdd_osc row u u2 n.c. u3 emc_cke0 u4 emc_d[0] u5 emc_d[3] u6 emc_d[9] u7 emc_d[12] u8 emc_d[15] u9 emc_d[19]/p2[0] u10 emc_d[22]/p2[3] u11 emc_d[2 6]/p2[7] u12 emc_d[30]/p2[11] u13 emc_cs0 u14 emc_bls[0] u15 adin0/ts_ym u16 ts_yp u17 n.c. row v v3 emc_d[4] v4 emc_d[5] v5 emc_d[8] v6 emc_d[10] v7 emc_d[13] v8 emc_d[16]/emc _dqs0 v9 emc_d[18]/emc_clk v10 emc_d[21]/p2[2] v11 emc_d[25]/p2[6] v12 emc_d[28]/p2[9] v13 emc_d[29]/p2[10] v14 emc_d[31]/p2[12] v15 emc_cs3 v16 adin2/ts_aux_in table 3. pin allocati on table (tfbga296) pin symbol pin symbol pin symbol
lpc3220_30_40_50 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 2.1 ? 24 june 2014 10 of 80 nxp semiconductors lpc3220/30/40/50 16/32-bit arm microcontrollers 6.2 pin description table 4. pin description symbol pin power supply domain type description adin0/ts_ym u15 vdd_ad analog in adc input 0/touch screen y minus adin1/ts_xm t14 vdd_ad analog in adc input 0/touch screen x minus adin2/ts_aux_in v16 vdd_ad analog in adc input 2/touch screen aux input dbgen g14 vdd_iod i: pd device test input low = jtag in-circuit debug available; normal operation. high = i/o cell boundary scan test; for board assembly bsdl test. emc_a[0]/p1[0] l3 vdd_emc i/o emc address bit 0 i/o port 1 gpio bit 0 emc_a[1]/p1[1] l4 vdd_emc i/o emc address bit 1 i/o port 1 gpio bit 1 emc_a[2]/p1[2] m1 vdd_emc i/o emc address bit 2 i/o port 1 gpio bit 2 emc_a[3]/p1[3] m2 vdd_emc i/o emc address bit 3 i/o port 1 gpio bit 3 emc_a[4]/p1[4] m3 vdd_emc i/o emc address bit 4 i/o port 1 gpio bit 4 emc_a[5]/p1[5] n1 vdd_emc i/o emc address bit 5 i/o port 1 gpio bit 5 emc_a[6]/p1[6] n2 vdd_emc i/o emc address bit 6 i/o port 1 gpio bit 6 emc_a[7/p1[7] n3 vdd_emc i/o emc address bit 7 i/o port 1 gpio bit 7 emc_a[8]/p1[8] m4 vdd_emc i/o emc address bit 8 i/o port 1 gpio bit 8 emc_a[9]/p1[9] p1 vdd_emc i/o emc address bit 9 i/o port 1 gpio bit 9 emc_a[10]/p1[10] p2 vdd_emc i/o emc address bit 10 i/o port 1 gpio bit 10 emc_a[11]/p1[11] p3 vdd_emc i/o emc address bit 11 i/o port 1 gpio bit 11 emc_a[12]/p1[12] n4 vdd_emc i/o emc address bit 12 i/o port 1 gpio bit 12 emc_a[13]/p1[13] r1 vdd_emc i/o emc address bit 13 i/o port 1 gpio bit 13 emc_a[14]/p1[14] r2 vdd_emc i/o emc address bit 14 i/o port 1 gpio bit 14
lpc3220_30_40_50 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 2.1 ? 24 june 2014 11 of 80 nxp semiconductors lpc3220/30/40/50 16/32-bit arm microcontrollers emc_a[15]/p1[15] l1 vdd_emc i/o emc address bit 15 i/o port 1 gpio bit 15 emc_a[16]/p1[16] k3 vdd_emc i/o emc address bit 16 i/o port 1 gpio bit 16 emc_a[17]/p1[17] k4 vdd_emc i/o emc address bit 17 i/o port 1 gpio bit 17 emc_a[18]/p1[18] k2 vdd_emc i/o emc address bit 18 i/o port 1 gpio bit 18 emc_a[19]/p1[19] k1 vdd_emc i/o emc address bit 19 i/o port 1 gpio bit 19 emc_a[20]/p1[20] j1 vdd_emc i/o emc address bit 20 i/o port 1 gpio bit 20 emc_a[21]/p1[21] j2 vdd_emc i/o emc address bit 21 i/o port 1 gpio bit 21 emc_a[22]/p1[22] j3 vdd_emc i/o emc address bit 22 i/o port 1 gpio bit 22 emc_a[23]/p1[23] j4 vdd_emc i/o emc address bit 23 i/o port 1 gpio bit 23 emc_bls[0] u14 vdd_emc o static memory byte lane 0 select emc_bls[1] t13 vdd_emc o static memory byte lane 1 select emc_bls[2] r12 vdd_emc o static memory byte lane 2 select emc_bls[3] p12 vdd_emc o static memory byte lane 3 select emc_cas r5 vdd_emc o sdram column address strobe out, active low emc_cke0 u3 vdd_emc o clock enable out for sdram bank 0 emc_cke1 l2 vdd_emc o clock enable out for sdram bank 1 emc_clk t3 vdd_emc o sdram clock out emc_clkin t4 vdd_emc i sdram clock feedback emc_cs0 u13 vdd_emc o emc static memory chip select 0 emc_cs1 r11 vdd_emc o emc static memory chip select 1 emc_cs2 t12 vdd_emc o emc static memory chip select 2 emc_cs3 v15 vdd_emc o emc static memory chip select 3 emc_d[0] u4 vdd_emc i/o: bk emc data bit 0 emc_d[1] r7 vdd_emc i/o: bk emc data bit 1 emc_d[2] t5 vdd_emc i/o: bk emc data bit 2 emc_d[3] u5 vdd_emc i/o: bk emc data bit 3 emc_d[4] v3 vdd_emc i/o: bk emc data bit 4 emc_d[5] v4 vdd_emc i/o: bk emc data bit 5 emc_d[6] t6 vdd_emc i/o: bk emc data bit 6 emc_d[7] r8 vdd_emc i/o: bk emc data bit 7 emc_d[8] v5 vdd_emc i/o: bk emc data bit 8 table 4. pin description ?continued symbol pin power supply domain type description
lpc3220_30_40_50 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 2.1 ? 24 june 2014 12 of 80 nxp semiconductors lpc3220/30/40/50 16/32-bit arm microcontrollers emc_d[9] u6 vdd_emc i/o: bk emc data bit 9 emc_d[10] v6 vdd_emc i/o: bk emc data bit 10 emc_d[11] t7 vdd_emc i/o: bk emc data bit 11 emc_d[12] u7 vdd_emc i/o: bk emc data bit 12 emc_d[13] v7 vdd_emc i/o: bk emc data bit 13 emc_d[14] t8 vdd_emc i/o: bk emc data bit 14 emc_d[15] u8 vdd_emc i/o: bk emc data bit 15 emc_d[16]/ emc_dqs0 v8 vdd_emc i/o: bk emc data bit 16 i/o: bk ddr data strobe 0 emc_d[17]/ emc_dqs1 r9 vdd_emc i/o: bk emc data bit 17 i/o: bk ddr data strobe 1 emc_d[18]/ emc_clk v9 vdd_emc i/o: p emc data bit 18 i/o: p ddr inverted clock output emc_d[19]/p2[0] u9 vdd_emc i/o: p emc data bit 19 i/o: p port 2 gpio bit 0 emc_d[20]/p2[1] t9 vdd_emc i/o: p emc data bit 20 i/o: p port 2 gpio bit 1 emc_d[21]/p2[2] v10 vdd_emc i/o: p emc data bit 21 i/o: p port 2 gpio bit 2 emc_d[22]/p2[3] u10 vdd_emc i/o: p emc data bit 22 i/o: p port 2 gpio bit 3 emc_d[23]/p2[4] t10 vdd_emc i/o: p emc data bit 23 i/o: p port 2 gpio bit 4 emc_d[24]/p2[5] r10 vdd_emc i/o: p emc data bit 24 i/o: p port 2 gpio bit 5 emc_d[25]/p2[6] v11 vdd_emc i/o: p emc data bit 25 i/o: p port 2 gpio bit 6 emc_d[26]/p2[7] u11 vdd_emc i/o: p emc data bit 26 i/o: p port 2 gpio bit 7 emc_d[27]/p2[8] t11 vdd_emc i/o: p emc data bit 27 i/o: p port 2 gpio bit 8 emc_d[28]/p2[9] v12 vdd_emc i/o: p emc data bit 28 i/o: p port 2 gpio bit 9 emc_d[29]/p2[10] v13 vdd_emc i/o: p emc data bit 29 i/o: p port 2 gpio bit 10 emc_d[30]/p2[11] u12 vdd_emc i/o: p emc data bit 30 i/o: p port 2 gpio bit 11 emc_d[31]/p2[12] v14 vdd_emc i/o: p emc data bit 31 i/o: p port 2 gpio bit 12 emc_dqm[0] r3 vdd_emc o sdram data mask 0 out table 4. pin description ?continued symbol pin power supply domain type description
lpc3220_30_40_50 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 2.1 ? 24 june 2014 13 of 80 nxp semiconductors lpc3220/30/40/50 16/32-bit arm microcontrollers emc_dqm[1] p4 vdd_emc o sdram data mask 1 out emc_dqm[2] t1 vdd_emc o sdram data mask 2 out emc_dqm[3] p5 vdd_emc o sdram data mask 3 out emc_dycs0 r6 vdd_emc o sdram active low chip select 0 emc_dycs1 g1 vdd_emc o sdram active low chip select 1 emc_oe h1 vdd_emc o emc static memory output enable emc_ras t2 vdd_emc o sdram row address strobe, active low emc_wr r4 vdd_emc o emc write strobe, active low flash_ale d2 vdd_ioc o flash address latch enable flash_ce e3 vdd_ioc o flash chip enable flash_cle f3 vdd_ioc o flash command latch enable flash_io[0] h2 vdd_ioc i/o: bk flash data bus, bit 0 flash_io[1] h3 vdd_ioc i/o: bk flash data bus, bit 1 flash_io[2] f1 vdd_ioc i/o: bk flash data bus, bit 2 flash_io[3] e1 vdd_ioc i/o: bk flash data bus, bit 3 flash_io[4] h4 vdd_ioc i/o: bk flash data bus, bit 4 flash_io[5] g2 vdd_ioc i/o: bk flash data bus, bit 5 flash_io[6] g3 vdd_ioc i/o: bk flash data bus, bit 6 flash_io[7] e2 vdd_ioc i/o: bk flash data bus, bit 7 flash_rd c1 vdd_ioc o flash read enable flash_rdy d1 vdd_ioc i flash ready (from flash device) flash_wr f2 vdd_ioc o flash write enable gpi_0/i2s1rx_sda c16 vdd_iod i general purpose input 0 i i 2 s1 receive data gpi_1/service c15 vdd_iod i general purpose input 1 i boot select input gpi_2/cap2[0]/ enet_rxd3 c14 vdd_iod i general purpose input 2 i timer 2 capture input 0 i ethernet receive data 3 (lpc3240 and lpc3250 only) gpi_3 f4 vdd_ioc i general purpose input 3 gpi_4/spi1_busy e13 vdd_iod i general purpose input 4 i spi1 busy input gpi_5/u3_dcd n16 vdd_ioa i general purpose input 5 i uart 3 data carrier detect input gpi_6/ hstim_cap/ enet_rxd2 c7 vdd_iob i: bk general purpose input 6 i: bk high-speed timer capture input i : bk ethernet receive data 2 (lpc3240 and lpc3250 only) table 4. pin description ?continued symbol pin power supply domain type description
lpc3220_30_40_50 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 2.1 ? 24 june 2014 14 of 80 nxp semiconductors lpc3220/30/40/50 16/32-bit arm microcontrollers gpi_7/cap4[0]/ mcabort d13 vdd_iod i general purpose input 7 i timer 4 capture input 0 i motor control pwm low-active fast abort input gpi_8/key_col6/ spi2_busy/ enet_rx_dv b16 vdd_iod i general purpose input 8 i keyscan column 6 input i spi2 busy input i ethernet receive data valid input (lpc3240 and lpc3250 only) gpi_9/key_col7/ enet_col e12 vdd_iod i general purpose input 9 i keyscan column 7 input i ethernet collision input (lpc3240 and lpc3250 only) gpi_19/u4_rx b15 vdd_iod i general purpose input 19 i uart 4 receive gpi_28/u3_ri n17 vdd_ioa i general purpose input 28 i uart 3 ring indicator input gpio_0 a12 vdd_iod i/o general purpose input/output 0 gpio_1 a11 vdd_iod i/o general purpose input/output 1 gpio_2/ key_row6/ enet_mdc d9 vdd_iod i/o general purpose input/output 2 o keyscan row 6 output o ethernet phy interface clock (lpc3240 and lpc3250 only) gpio_3/ key_row7/ enet_mdio c11 vdd_iod i/o general purpose input/output 3 i/o keyscan row 7 output i/o ethernet phy interface data (lpc3240 and lpc3250 only) gpio_4/ ssel1/ lcdvd[22] b11 vdd_iod i/o general purpose input/output 4 i/o ssp1 slave select i/o lcd data bit 22 (lpc3230 and lpc3250 only) gpio_5/ ssel0/ mci0 e9 vdd_iod i/o general purpose input/output 5 i/o ssp0 slave select i/o motor control channel 0 input gpo_0/ tst_clk1 c3 vdd_ioc o general purpose output 0 o test clock 1 out gpo_1 d4 vdd_ioc o general purpose output 1 gpo_2/ mat1[0]/ lcdvd[0] b14 vdd_iod o general purpose output 2 o timer 1 match output 0 o lcd data bit 0 (lpc3230 and lpc3250 only) gpo_3/ lcdvd[1] d12 vdd_iod o general purpose output 3 o lcd data bit 1 (lpc3230 and lpc3250 only) gpo_4 d8 vdd_iob o general purpose output 4 table 4. pin description ?continued symbol pin power supply domain type description
lpc3220_30_40_50 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 2.1 ? 24 june 2014 15 of 80 nxp semiconductors lpc3220/30/40/50 16/32-bit arm microcontrollers gpo_5 b3 vdd_ioc o general purpose output 5 gpo_6/ lcdvd[18] a16 vdd_iod o general purpose output 6 o lcd data bit 18 (lpc3230 and lpc3250 only) gpo_7/ lcdvd[2] a15 vdd_iod o general purpose output 7 o lcd data bit 2 (lpc3230 and lpc3250 only) gpo_8/ lcdvd[8] c13 vdd_iod o general purpose output 8 o lcd data bit 8 (lpc3230 and lpc3250 only) gpo_9/ lcdvd[9] c12 vdd_iod o general purpose output 9 o lcd data bit 9 (lpc3230 and lpc3250 only) gpo_10/ mcob2/ lcdpwr e11 vdd_iod o general purpose output 10 o motor control pwm channel 2, output b o lcd panel power enable (lpc3230 and lpc3250 only) gpo_11 e8 vdd_iob o general purpose output 11 gpo_12/ mcoa2/ lcdle b12 vdd_iod o general purpose output 12 o motor control pwm channel 2, output a o lcd line end signal (lpc3230 and lpc3250 only) gpo_13/ mcob1/ lcddclk b13 vdd_iod o general purpose output 13 o motor control pwm channel 1, output b o lcd clock output (lpc3230 and lpc3250 only) gpo_14 d3 vdd_ioc o general purpose output 14 gpo_15/ mcoa1/ lcdfp a14 vdd_iod o general purpose output 15 o motor control pwm channel 1, output a o lcd frame/sync pulse (lpc3230 and lpc3250 only) gpo_16/ mcob0/ lcdenab/lcdm d10 vdd_iod o general purpose output 16 o motor control pwm channel 0, output b o lcd stn ac bias/tft data enable (lpc3230 and lpc3250 only) gpo_17 n18 vdd_ioa o general purpose output 17 gpo_18/ mcoa0/ lcdlp d11 vdd_iod o general purpose output 18 o motor control pwm channel 0, output a o lcd line sync/horizontal sync (lpc3230 and lpc3250 only) gpo_19 c2 vdd_ioc o general purpose output 19 gpo_20 b2 vdd_ioc o general purpose output 20 gpo_21/ u4_tx/ lcdvd[3] a13 vdd_iod o general purpose output 21 o uart 4 transmit o lcd data bit 3 (lpc3230 and lpc3250 only) table 4. pin description ?continued symbol pin power supply domain type description
lpc3220_30_40_50 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 2.1 ? 24 june 2014 16 of 80 nxp semiconductors lpc3220/30/40/50 16/32-bit arm microcontrollers gpo_22/ u7_hrts/ lcdvd[14] e10 vdd_iod o general purpose output 22 o hs uart 7 rts out o lcd data bit 14 (lpc3230 and lpc3250 only) gpo_23/ u2_hrts/ u3_rts m16 vdd_ioa o general purpose output 23 oh s u a r t 2 r t s o u t o uart 3 rts out highcore/ lcdvd[17] h16 vdd_iod o core voltage control out o lcd data bit 17 (lpc3230 and lpc3250 only) i2c1_scl a5 vdd_iob i/o t i 2 c1 serial clock input/output i2c1_sda b6 vdd_iob i/o t i 2 c1 serial data input/output i2c2_scl a3 vdd_ioc i/o t i 2 c2 serial clock input/output i2c2_sda e4 vdd_ioc i/o t i 2 c2 serial data input/output i2s1tx_clk/ mat3[0] a4 vdd_iob i/o i 2 s1 transmit clock o timer 3 match output 0 i2s1tx_sda/ mat3[1] e7 vdd_iob i/o i 2 s1 transmit data o timer 3 match output 1 i2s1tx_ws/ cap3[0] b4 vdd_iob i/o i 2 s1 transmit word select i/o timer 3 capture input 0 jtag_ntrst h17 vdd_iod i: pu jtag1 reset input. must be low during power-on reset. see section 12.1 ? connecting the jtag_ntrst pin ? . jtag_rtck h18 vdd_iod o jtag1 return clock out jtag_tck h14 vdd_iod i jtag1 clock input jtag_tdi j16 vdd_iod i: pu jtag1 data input jtag_tdo j15 vdd_iod o jtag1 data out jtag_tms g18 vdd_iod i: pu tag1 test mode select input key_col0/ enet_tx_clk f15 vdd_iod i keyscan column 0 input i ethernet transmit clock (lpc3240 and lpc3250 only) key_col1/ enet_rx_clk/ enet_ref_clk e16 vdd_iod i keyscan column 1 input i ethernet receive clock (mii mode, lpc3240 and lpc3250 only) i ethernet reference clock (rmii mode, lpc3240 and lpc3250 only) key_col2/ enet_rx_er d17 vdd_iod i keyscan column 2 input i ethernet receive error input (lpc3240 and lpc3250 only) key_col3/ enet_crs d18 vdd_iod i keyscan column 3 input i ethernet carrier sense input (lpc3240 and lpc3250 only) table 4. pin description ?continued symbol pin power supply domain type description
lpc3220_30_40_50 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 2.1 ? 24 june 2014 17 of 80 nxp semiconductors lpc3220/30/40/50 16/32-bit arm microcontrollers key_col4/ enet_rxd0 g15 vdd_iod i keyscan column 4 input i ethernet receive data 0 (lpc3240 and lpc3250 only) key_col5/ enet_rxd1 f16 vdd_iod i keyscan column 5 input i ethernet receive data 1 (lpc3240 and lpc3250 only) key_row0/ enet_tx_er e15 vdd_iod i/o t keyscan row 0 out i/o t ethernet transmit error (lpc3240 and lpc3250 only) key_row1/ enet_txd2 e14 vdd_iod i/o t keyscan row 1 out i/o t ethernet transmit data 2 (lpc3240 and lpc3250 only) key_row2/ enet_txd3 f14 vdd_iod i/o t keyscan row 2 out i/o t ethernet transmit data 3 (lpc3240 and lpc3250 only) key_row3/ enet_tx_en d16 vdd_iod i/o t keyscan row 3 out i/o t ethernet transmit enable (lpc3240 and lpc3250 only) key_row4/ enet_txd0 c17 vdd_iod i/o t keyscan row 4 out i/o t ethernet transmit data 0 (lpc3240 and lpc3250 only) key_row5/ enet_txd1 c18 vdd_iod i/o t keyscan row 5 out i/o t ethernet transmit data 1 (lpc3240 and lpc3250 only) ms_bs/mat2[1] a6 vdd_iod i/o: p ms/sd card command out o timer 2 match output 1 ms_dio0/mat0[0] a8 vdd_iod i/o: p ms/sd card data 0 o timer 0 match output 0 ms_dio1/ mat0[1] a7 vdd_iod i/o: p ms/sd card data 1 o timer 0 match output 1 ms_dio2/ mat0[2] b8 vdd_iod i/o: p ms/sd card data 2 o timer 0 match output 2 ms_dio3/ mat0[3] c8 vdd_iod i/o: p ms/sd card data 3 o timer 0 match output 3 ms_sclk/ mat2[0] b7 vdd_iod i/o ms/sd card clock output o timer 2 match output 0 n.c. b17, u17, u2 - - not connected onsw m15 vdd_rtc o rtc match output for external power control p0[0]/ i2s1rx_clk b5 vdd_iob i/o port 0 gpio bit 0 i/o i 2 s1 receive clock table 4. pin description ?continued symbol pin power supply domain type description
lpc3220_30_40_50 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 2.1 ? 24 june 2014 18 of 80 nxp semiconductors lpc3220/30/40/50 16/32-bit arm microcontrollers p0[1]/ i2s1rx_ws d7 vdd_iob i/o port 0 gpio bit 1 i/o i 2 s1 receive word select p0[2]/ i2s0rx_sda/ lcdvd[4] m17 vdd_ioa i/o port 0 gpio bit 2 i/o i 2 s0 receive data i/o lcd data bit 4 (lpc3230 and lpc3250 only) p0[3]/ i2s0rx_clk/ lcdvd[5] m18 vdd_ioa i/o port 0 gpio bit 3 i/o i 2 s0 receive clock i/o lcd data bit 5 (lpc3230 and lpc3250 only) p0[4]/ i2s0rx_ws/ lcdvd[6] l15 vdd_ioa i/o port 0 gpio bit 4 i/o i 2 s0 receive word select i/o lcd data bit 6 (lpc3230 and lpc3250 only) p0[5]/ i2s0tx_sda/ lcdvd[7] l16 vdd_ioa i/o port 0 gpio bit 5 i/o i 2 s0 transmit data i/o lcd data bit 7 (lpc3230 and lpc3250 only) p0[6]/ i2s0tx_clk/ lcdvd[12] l17 vdd_ioa i/o port 0 gpio bit 6 i/o i 2 s0 transmit clock i/o lcd data bit 12 (lpc3230 and lpc3250 only) p0[7]/ i2s0tx_ws/ lcdvd[13] l18 vdd_ioa i/o port 0 gpio bit 7 i/o i 2 s0 transmit word select i/o lcd data bit 13 (lpc3230 and lpc3250 only) pll397_loop r14 vdd_pll397 analog filter pll397 loop filter (for external components) pwm_out1/ lcdvd[16] d14 vdd_iod o pwm1 out o lcd data bit 16 (lpc3230 and lpc3250 only) pwm_out2/intstat/ lcdvd[19] d15 vdd_iod o pwm2 output/i nternal interrupt status [1] o lcd data bit 19 (lpc3230 and lpc3250 only) reset m14 vdd_rtc i reset input, active low resout g4 vdd_ioc o reset out. reflec ts external and wdt reset rtcx_in p16 vdd_rtc analog in rtc oscillator input rtcx_out p17 vdd_rtc analog out rtc oscillator output spi1_clk/ sck0 c9 vdd_iod o spi1 clock out o ssp0 clock out spi1_datin/ miso0/ gpi_25/ mci1 c10 vdd_iod i/o spi1 data in i/o ssp0 miso i/o general purpose input bit 25 i motor control channel 1 input spi1_datio/ mosi0/ mci2 b9 vdd_iod i/o spi1 data out (and optional input) i/o ssp0 mosi i motor control channel 2 input table 4. pin description ?continued symbol pin power supply domain type description
lpc3220_30_40_50 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 2.1 ? 24 june 2014 19 of 80 nxp semiconductors lpc3220/30/40/50 16/32-bit arm microcontrollers spi2_clk/ sck1/ lcdvd[23] b10 vdd_iod i/o spi2 clock out i/o ssp1 clock out i/o lcd data bit 23 (lpc3230 and lpc3250 only) spi2_datio/ mosi1/ lcdvd[20] a9 vdd_iod i/o spi2 data out (and optional input) i/o ssp1 mosi i/o lcd data bit 20 (lpc3230 and lpc3250 only) spi2_datin/ miso1/ lcdvd[21]/ gpi_27 a10 vdd_iod i/o spi2 data in i/o ssp1 miso i/o lcd data 21 (lpc3230 and lpc3250 only) i/o general purpose input bit 27 sysclken/ lcdvd[15] g17 vdd_iod i/o t clock request out for external clock source i/o t lcd data bit 15 (lpc3230 and lpc3250 only) sysx_in t17 vdd_osc analog in system clock oscillator input sysx_out r15 vdd_osc analog out system clock oscillator output ts_xp r13 vdd_ad i/o touchscreen x output ts_yp u16 vdd_ad i/o touchscreen y output tst_clk2 c6 vdd_iob o test clock 2 out u1_rx/cap1[0]/ gpi_15 k15 vdd_ioa i/o hs uart 1 receive i/o timer 1 capture input 0 i/o general purpose input bit 15 u1_tx k16 vdd_ioa o hs uart 1 transmit u2_hcts/ u3_cts/gpi_16 j18 vdd_ioa i/o hs uart 2 clear to send input i uart 3 clear to send i/o general purpose input bit 16 u2_rx/ u3_dsr/gpi_17 k18 vdd_ioa i/o hs uart 2 receive i/o uart 3 data set ready i/o general purpose input bit 17 u2_tx/u3_dtr k17 vdd_ioa o hs uart 2 transmit o uart 3 data terminal ready out u3_rx/ gpi_18 j14 vdd_iod i/o uart 3 receive i/o general purpose input bit 18 u3_tx j17 vdd_iod o uart 3 transmit u5_rx/ gpi_20 f18 vdd_iod i/o uart 5 receive i general purpose input bit 20 u5_tx h15 vdd_iod o uart 5 transmit u6_irrx/ gpi_21 f17 vdd_iod i/o uart 6 receive (with irda) i general purpose input bit 21 u6_irtx g16 vdd_iod o uart 6 transmit (with irda) table 4. pin description ?continued symbol pin power supply domain type description
lpc3220_30_40_50 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 2.1 ? 24 june 2014 20 of 80 nxp semiconductors lpc3220/30/40/50 16/32-bit arm microcontrollers u7_hcts/ cap0[1]/ lcdclkin/ gpi_22 g13 vdd_iod i hs uart 7 cts in i timer 0 capture input 1 i lcd panel clock in (lpc3230 and lpc3250 only) i general purpose input bit 22 u7_rx/ cap0[0]/ lcdvd[10]/ gpi_23 e17 vdd_iod i/o hs uart 7 receive i/o timer 0 capture input 0 i/o lcd data bit 10 (lpc3230 and lpc3250 only) i/o general purpose input bit 23 u7_tx/ mat1[1]/ lcdvd[11] e18 vdd_iod o hs uart 7 transmit o timer 1 match output 1 o lcd data bit 11 (lpc3230 and lpc3250 only) usb_atx_int c4 vdd_ioc i interrupt from usb atx usb_dat_vp/ u5_rx d5 vdd_ioc i/o: p usb transmit data, d+ receive i/o: p uart 5 receive usb_i2c_scl e5 vdd_ioc i/o t i 2 c clock for usb atx interface usb_i2c_sda e6 vdd_ioc i/o t i 2 c data for usb atx interface usb_oe_tp d6 vdd_ioc i/o usb transmit enable for dat/se0 usb_se0_vm/ u5_tx c5 vdd_ioc i/o: p usb single ended zero transmit, d ? receive i/o: p uart 5 transmit vdd_ad n12, n13 vdd_ad power 3.3 v supply for adc/touch screen vdd_core g7, g9, g11, j7, j12, m7, m11 vdd_core power 1.2 v or 0.9 v supply for core vdd_corefxd l12, m13 vdd_corefxd power fixed 1.2 v supply for digital portion of the analog block vdd_emc j6, k6, k7, l6, m6, m8, n7, n8, n9, n10, n11 vdd_emc power 1.8 v or 2.5 v or 3.3 v supply for external memory controller (emc) vdd_ioa h13, j13 vdd_ioa power 1.8 v or 3.3 v supply for ioa domain vdd_iob f8 vdd_iob power 1.8 v or 3.3 v supply for iob domain table 4. pin description ?continued symbol pin power supply domain type description
lpc3220_30_40_50 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 2.1 ? 24 june 2014 21 of 80 nxp semiconductors lpc3220/30/40/50 16/32-bit arm microcontrollers vdd_ioc f7, g6, h6, j5 vdd_ioc power 1.8 v or 3.3 v supply for ioc domain vdd_iod f13, f9 vdd_iod power 1.8 v to 3.3 v supply for iod domain vdd_osc t18 vdd_osc power 1.2 v supply for main oscillator vdd_pll397 t16 vdd_pll397 power 1.2 v supply for 397x pll vdd_pllhclk r17 vdd_pllhclk power 1.2 v supply for hclk pll vdd_pllusb p15 vdd_pllusb power 1.2 v supply for usb pll vdd_fuse n14 vdd_fuse power 1.2 v supply vdd_rtc k14 vdd_rtc power 1.2 v supply for rtc i/o vdd_rtccore l13 vdd_rtccore power 1.2 v supply for rtc vdd_rtcosc n15 vdd_rtcosc power 1.2 v supply for rtc oscillator vss_ad p13 - power ground for adc/touch screen vss_core g8, g10, g12, h7, k12, l7, m9, m10, m12 - power ground for core vss_emc k5, l5, m5, n5, n6, p6, p7, p8, p9, p10, p11 - power ground for emc vss_ioa k13 - power ground vdd_ioa domain vss_iob f6 - power ground vdd_iob domain vss_ioc f5, g5, h5 - power ground vdd_ioc domain vss_iod f10, f11, f12, h12 - power ground vdd_iod domain vss_osc p14 - power ground for main oscillator vss_pll397 t15 - power ground for 397x pll vss_pllhclk r18 - power ground for hclk pll table 4. pin description ?continued symbol pin power supply domain type description
lpc3220_30_40_50 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 2.1 ? 24 june 2014 22 of 80 nxp semiconductors lpc3220/30/40/50 16/32-bit arm microcontrollers [1] the pwm2_ctrl register cont rols this pin function (see lpc32x0 user manual ). [1] see lpc32x0 user manual for details. vss_pllusb r16 - power ground for usb pll vss_rtccore l14 - power ground for rtc vss_rtcosc p18 - power ground for rtc oscillator table 4. pin description ?continued symbol pin power supply domain type description table 5. digital i/o pad types [1] parameter abbreviation i/o type i = input. o = output. i/o = bidirectional. i/o t = bidirectional or high impedance. pin detail bk: pin has a bus keeper functi on that weakly retains the last logic level driven on an i/o pin. bus keeper current for different i/o pin voltages: 0 v= 1 ? a (max) vdd_x = 1 ? a (max) 2/3 ? vdd_x = 55 ? a (max) 1/3 ? vdd_x = 60 ? a (max) pu: pin has a nominal 50 ? a internal pull-up connected. pd: pin has a nominal 50 ? a internal pull-down connected. p: pin has programmable input characteristics. table 6. supply domains supply domain voltage range related supply pins description vdd_core 0.9 v to 1.39 v vdd_core core power domain. vdd_corefxd 1.2 v vdd_corefxd fixed 1.2 v supply for digital portion of the analog block. other core domains 1.2 v vdd_pll397, vdd_pllhclk, vdd_pllusb, vdd_fuse, vdd_osc 1.2 v supplies, tied to vdd_corefxd. vdd_rtc 0.9 v to 1.39 v vdd_rtc, vdd_rtccore, vdd_rtcosc rtc supply domain. can be connected to a battery backed-up power source. vdd_ad 2.7 v to 3.6 v vdd_ad 3.3 v supply for adc and touch screen. vdd_emc 1.7 v to 1.95 v 2.3 v to 2.7 v 2.7 v to 3.6 v vdd_emc external memory interface io pins in 1.8 v range, 2.5 v range, or 3.3 v range.
lpc3220_30_40_50 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 2.1 ? 24 june 2014 23 of 80 nxp semiconductors lpc3220/30/40/50 16/32-bit arm microcontrollers [1] the vdd_ioa, vdd_iob, vdd_ioc, and vdd_ iod supply domains can be operated at a voltage independent of the other domains as long as all pins connected to the same peripheral are at the same voltage level. there are two special cases for dete rmining supply domain voltages (for details see application note an10777 ): a) ethernet configured in mii mode: vdd_iod must be the same as vdd_iob. b) uart 3 when used with hardware flow control or when sharing an rs-232 transceiver with another uart: vdd_ioa must be the same as vdd_iod. vdd_ioa [1] 1.7 v to 1.95 v or 2.7 v to 3.6 v vdd_ioa peripheral supply. vdd_iob [1] 1.7 v to 1.95 v or 2.7 v to 3.6 v vdd_iob peripheral supply. vdd_ioc [1] 1.7 v to 1.95 v or 2.3 v to 3.6 v vdd_ioc peripheral supply. vdd_iod [1] 1.7 v to 1.95 v or 2.7 v to 3.6 v vdd_iod peripheral supply. table 6. supply domains supply domain voltage range related supply pins description
lpc3220_30_40_50 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 2.1 ? 24 june 2014 24 of 80 nxp semiconductors lpc3220/30/40/50 16/32-bit arm microcontrollers 7. functional description 7.1 cpu and subsystems 7.1.1 cpu nxp created the lpc3220/30/40/50 using an arm926ej-s cpu core that includes a harvard architecture and a 5-stage pipeline. to this arm core, nxp implemented a 32 kb instruction cache, a 32 kb data cache and a vector floating point coprocessor. the arm926ej-s core also has an integral memory management unit (mmu) to provide the virtual memory capabilities required to support the mu lti-programming demands of modern operating systems. the basic arm926e j-s core v5te instruction set includes dsp instruction extensions for native jazelle java byte-code execution in hardware. the lpc3220/30/40/50 operates at cpu frequencies up to 266 mhz. 7.1.2 vector floating point (vfp) coprocessor the lpc3220/30/40/50 includes a vfp co-processor providing full support for single-precision and double-precision add, subtract, multiply, divide, and multiply-accumulat e operations at cpu cl ock speeds. it is compliant with the ieee 754 standard for binary floating-point arithmetic. this hardware floating point capability makes the microcontroller suitable for advanced motor control and dsp applications. the vfp has 3 separate pipelines for floating-point mac operations, divide or square root operations, and load/store operations. thes e pipelines operate in parallel and can complete execution out of order. all single-pr ecision instructions execute in one cycle, except the divide and square root instructions. all double-precision multiply and multiply-accumulate instruct ions take two cycles. the vfp also provides format conversions between floating-point and integer word formats. 7.1.3 emulation and debugging the lpc3220/30/40/50 supports emulation and debugging via a dedicated jtag serial port. an embedded trace buffer allows tracing program execution. the dedicated jtag port allows debugging of all chip features wit hout impact to any pins that may be used in the application. 7.1.3.1 embedded ice standard arm embeddedice logic provides on-chip debug support. the debugging of the target system requires a host computer running the debugger software and an embedded ice protocol converter. the embedded ice protocol converter converts the remote debug protocol commands to the jtag data needed to access the arm core. the arm core has a debug communication channel (dcc) function built-in. the debug communication channel allows a program running on the target to communicate with the host debugger or another separate host without stopping the program flow or entering the debug state.
lpc3220_30_40_50 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 2.1 ? 24 june 2014 25 of 80 nxp semiconductors lpc3220/30/40/50 16/32-bit arm microcontrollers 7.1.3.2 embedded trace buffer the embedded trace module (etm) is connecte d directly to the arm core. it compresses the trace information and exports it through a narrow trace port. an internal embedded trace buffer (etb) of 2048 ? 24 bits captures the trace information under software debugger control. data from the etb is recovered by the debug software through the jtag port. the trace contains information about when the arm core switches between states. instruction shows the flow of execution of the processor and provides a list of all the instructions that were executed. instruction trace is significantly compressed by only broadcasting branch addresses as well as a set of status signals that indicate the pipeline status on a cycle by cycle basis. for data accesses either data or address or both can be traced. 7.2 ahb matrix the lpc3220/30/40/50 has a multi-layer ahb matrix for inter-blo ck communication. ahb is an arm defined high-speed bus, which is part of the arm bus architecture. ahb is a high-bandwidth low-latency bus that supports multi-master arbitration and a bus grant/request mechanism. for systems that ha ve only one (cpu), or two (cpu and dma) bus masters a simple ahb works well. however, if a system r equires multiple bus masters and the cpu needs access to external memory, a single ahb bus can cause a bottleneck. to increase performance, the lpc3220/30/40/50 uses an expanded ahb architecture known as multi-layer ahb. a multi-layer ahb replaces the request/grant and arbitration mechanism used in a simple ahb with an interconnect matrix that moves arbitration out toward the slave devices. thus, if a cpu and a dma controller want access to the same memory, the interconnect matrix arbitrates between the two when granting access to the memory. this advanced architecture allows simultaneous access by bus masters to different resources with an increase in arbitration complexity. in this architectural implementation, removing guaranteed central arbitration and allowing more than one bus master to be active at the same time provides better overall microcontroller performance. in the lpc3220/30/40/50, the multi-layer ah b system has a separate bus for each of seven ahb masters: ? cpu data bus ? cpu instruction bus ? general purpose dma master 0 ? general purpose dma master 1 ? ethernet controller ? usb controller ? lcd controller there are no arbitration delays unless two mast ers attempt to access the same slave at the same time.
lpc3220_30_40_50 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 2.1 ? 24 june 2014 26 of 80 nxp semiconductors lpc3220/30/40/50 16/32-bit arm microcontrollers 7.2.1 apb many peripheral functions are accessed by on-chip apbs that are attached to the higher speed ahb. the apb performs reads and writes to peripheral registers in three peripheral clocks. 7.2.2 fab some peripherals are placed on a special bu s called fab that allows faster cpu access to those peripheral functions. a write access to fab peripherals takes a single ahb clock and a read access to fab peripherals takes two ahb clocks. 7.3 physical memory map the physical memory map incorporates se veral distinct regions, as shown in figure 3 . when an application is running, the cpu interrupt vectors are re-mapped to allow them to reside in on-chip sram (iram).
lpc3220_30_40_50 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 2.1 ? 24 june 2014 27 of 80 nxp semiconductors lpc3220/30/40/50 16/32-bit arm microcontrollers fig 3. lpc3220/30/40/50 memory map on-chip memory 0x4000 0000 0x0000 0000 0.0 gb 768 mb 1.0 gb 4.0 gb peripherals on ahb matrix slave port 5 0x0fff ffff 0x2000 0000 0x3000 0000 0x2fff ffff 0x1fff ffff 0x8000 0000 0xffff ffff 0x1000 0000 0x3fff ffff 0x4fff ffff 0x5000 0000 0x7fff ffff peripherals on ahb matrix slave port 6 peripherals on ahb matrix slave port 7 off-chip memory irom or iram 0x0000 0000 to 0x03ff ffff dummy space for dma 0x 0400 0000 to 0x07ff ffff iram 0x0800 0000 to 0x0bff ffff irom 0x0c00 0000 to 0x0 fff ffff ahb peripherals 0x2000 0000 to 0x2007 ffff ahb peripherals 0x200a 0000 to 0x200b ffff apb peri pherals 0x2008 0000 to 0x2009 ffff reserved ahb peripherals 0x3000 0000 to 0x31ff ffff reserved fab peripherals 0x4000 0000 to 0x4007 ffff apb peri pherals 0x4008 0000 to 0x400f ffff reserved reserved reserved reserved reserved 0x9fff ffff 0xa000 0000 0xbfff ffff 0xc000 0000 0xdfff ffff 0xe000 0000 0xe0ff ffff 0xe100 0000 0xe1ff ffff 0xe200 0000 0xe2ff ffff 0xe300 0000 0xe3ff ffff 0xe400 0000 2.0 gb emc_dycs0 emc_dycs1 emc_cs0 emc_cs1 emc_cs2 emc_cs3 002aae468
lpc3220_30_40_50 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 2.1 ? 24 june 2014 28 of 80 nxp semiconductors lpc3220/30/40/50 16/32-bit arm microcontrollers 7.4 internal memory 7.4.1 on-chip rom the built-in 16 kb rom contains a program which runs a boot procedure to load code from one of four external sources, uart 5, ssp0 (spi mo de), emc static cs0 memory, or nand flash. after reset, execution always begins from the internal rom. the bootstrap software first reads the service input (gpi_1 ). if service is low, the bootstrap starts a service boot and can download a program over serial link uart 5 to iram and transfer execution to the downloaded code. if the service pin is high, the bootstrap routine jumps to normal boot. the normal boot process first tests spi memory for boot informat ion if present it uploads the boot code and transfers execution to the uploaded software. if the spi is not present or no software is loaded, the bootloader will test the emc static cs0 memory for the presence of boot code and if present boots from static memory, if this test fails the boot loader will test external nand flash for boot code and boot if code is present. the boot loader consumes no user memory space because it is in rom. 7.4.2 on-chip sram on-chip sram may be used for code and/or data storage. the sram may be accessed as 8, 16, or 32 bit memory. the lpc3220/30/ 40/50 provides 256 kb of internal sram. 7.5 external memory interfaces the lpc3220/30/40/50 includes three ex ternal memory interfaces, nand flash controllers, secure digital me mory controller, and an external memory controller for sdram, ddr sdram, and static memory devices. 7.5.1 nand flash controllers the lpc3220/30/40/50 includes two nand flash controllers, one for multi-level cell nand flash devices and one for single-lev el cell nand flash devices. the two nand flash controllers use the same pins to interf ace to external nand flash devices, so only one interface is active at a time. 7.5.1.1 multi-level cell (mlc) nand flash controller the mlc nand flash controller inte rfaces to either multi-leve l or single-level nand flash devices. an external nand flash device is us ed to allow the bootloader to automatically load a portion of the application code into internal sram for execution following reset. the mlc nand flash controller supports sma ll (528 byte) and large (2114 byte) pages. programmable nand timing parameters allo w support for a variety of nand flash devices. a built-in reed-solomon encoder/ decoder provides error detection and correction capability. a 528 byte data buffer reduces the need for cpu supervision during loading. the mlc nand flash contro ller also provides dma support.
lpc3220_30_40_50 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 2.1 ? 24 june 2014 29 of 80 nxp semiconductors lpc3220/30/40/50 16/32-bit arm microcontrollers 7.5.1.2 single-level cell (slc) nand flash controller the slc nand flash controller interfaces to single-level nand flash devices. dma page transfers are supported, including a 20-byte dma read and write fifo. hardware support for ecc (error checking and correction) is included for the main data area. software can correct a single bit error. 7.5.2 sd card controller the sd interface allows access to external sd memory cards. the sd card interface conforms to the sd memory card spec ification version 1.01 . 7.5.2.1 features ? 1-bit and 4-bit data line interface support. ? dma is supported through the system dma controller. ? provides all functions spec ific to the sd memory ca rd. these include the clock generation unit, power management control, command and data transfer. 7.5.3 external memory controller the lpc3220/30/40/50 includes a memory co ntroller that supports data bus sdram, ddr sdram, and static memory devices. th e memory controller provides an interface between the system bus and external (off-chip) memory devices. the controller supports 16-bit and 32-bit wide sdr sdram devices of 64 mbit, 128 mbit, 128 mbit, 256 mbit, and 512 mbit sizes, as well as 16-bit wide data bus ddr sdram devices of 64 mbit, 128 mbit, 128 mbit, 256 mbit, and 512 mbit sizes. two dynamic memory chip selects are supplied, supporting two groups of sdram: ? dycs0 in the address range 0x8000 0000 to 0x9fff ffff ? dycs1 in the address range 0xa000 0000 to 0xbfff ffff the memory controller also supports 8-bit, 16-bit, and 32-bit wide asynchronous static memory devices, including ram, rom, and flash, with or without asynchronous page mode. four static memory chip sele cts are supplied for sram devices: ? cs0 in the address range 0xe000 0000 to 0xe0ff ffff ? cs1 in the address range 0xe100 0000 to 0xe1ff ffff ? cs2 in the address range 0xe200 0000 to 0xe2ff ffff ? cs3 in the address range 0xe300 0000 to 0xe3ff ffff the sdram controller uses three data ports to allow simultaneous requests from multiple on-chip ahb bus masters and has the following features. ? dynamic memory interface su pports sdram, ddr-sdram, and low-power variants. ? read and write buffers to reduce latency and improve performance. ? static memory features include ? asynchronous page mode read ? programmable wait states ? bus turnaround cycles ? output enable and write enable delays
lpc3220_30_40_50 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 2.1 ? 24 june 2014 30 of 80 nxp semiconductors lpc3220/30/40/50 16/32-bit arm microcontrollers ? extended wait ? power-saving modes dynamically co ntrol emc_cke[1:0] and emc_clk. ? dynamic memory self-refresh mode supported by software. ? controller supports 2 k, 4 k, and 8 k row address synchronous memory parts. that is, typical 512 mb, 256 mb, 128 mb, and 16 mb parts, with 8, 16, or 32 data bits per device. ? two reset domains enable dynamic memory contents to be preserved over a soft reset. ? this controller does not support synchron ous static memory devices (burst mode devices). 7.6 ahb master peripherals the lpc3220/30/40/50 implements four ah b master peripherals, which include a general purpose direct memory access (g pdma) controller, a 10/100 ethernet media access controller (mac), a universal serial bu s (usb) controller, and an lcd controller. each of these four peripherals contain an in tegral dma controller optimized to support the performance demands of the peripheral. 7.6.1 general purpose dma (gpdma) controller the gpdma controller allows periphera l-to memory, memory-to-peripheral, peripheral-to-peripheral, and memory-to-memory transactions. each dma stream provides unidirectional serial dma transfer s for a single source and destination. for example, a bidirectional port requires one st ream for transmit and one for receive. the source and destination areas can each be either a memory region or a peripheral, and can be accessed through the same ahb master, or one area by each master. the dma controller supports the following peripheral device transfers. ? secure digital (sd) memory interface ? high-speed uarts ? i 2 s0 and i 2 s1 ports ? spi1 and spi2 interfaces ? ssp0 and ssp1 interfaces ? memory the dma controls eight dma channels with ha rdware prioritization. the dma controller interfaces to the system via two ahb bus masters, each with a full 32-bit data bus width. dma operations may be set up for 8-bit, 16-bit, and 32-bit data widths, and can be either big-endian or little-endian. incrementing or non-incrementing addressing for source and destination are supported, as well as programmable dma burst size. scatter or gather dma is supported through the use of linked lists. this means that the source and destination areas do not have to occupy contiguous areas of memory. 7.6.2 ethernet mac the ethernet block contains a full featured 10 mbit/s or 100 mbit/s ethernet mac designed to provide optimized performa nce through the use of dma hardware acceleration. features include a generous suite of control registers, half or full duplex operation, flow control, cont rol frames, hardware acceleration for transmit retry, receive
lpc3220_30_40_50 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 2.1 ? 24 june 2014 31 of 80 nxp semiconductors lpc3220/30/40/50 16/32-bit arm microcontrollers packet filtering and wake-up on lan activity. automatic frame transmission and reception with scatter-gather dma off-loads many oper ations from the cpu. the ethernet dma can access off-chip memory via the emc, as well as the iram. the ethernet block interfaces between an off-chip ethernet phy using t he media independent interface (mii) or reduced mii (rmii) protocol and the on-ch ip media independent interface management (miim) serial bus. 7.6.2.1 features ? ethernet standards support: ? supports 10 mbit/s or 100 mbit/s phy devices including 10 base-t, 100 base-tx, 100 base-fx, and 100 base-t4. ? fully compliant with ieee standard 802.3. ? fully compliant with 802.3x full duplex flow contro l and half duplex back pressure. ? flexible transmit and receive frame options. ? virtual local area network (vlan) frame support. ? memory management: ? independent transmit and receive buffers memory mapped to sram. ? dma managers with scatter/gather dma and arrays of frame descriptors. ? memory traffic optimized by buffering and pre-fetching. ? enhanced ethernet features: ? receive filtering. ? multicast and broadcast frame support for both transmit and receive. ? optional automatic frame check sequence (fcs) insertion with circular redundancy check (crc) for transmit. ? selectable automatic transmit frame padding. ? over-length frame support for both transmit and receive allows any length frames. ? promiscuous receive mode. ? automatic collision back-off and frame retr ansmission. ? includes power management by clock switching. wake-on-lan power management support allows system wake-u p using the receive filters or a magic frame detection filter. ? physical interface ? attachment of external phy chip through standard mii or rmii interface. ? phy register access is available via the miim interface. 7.6.3 usb interface the lpc3220/30/40/50 supports usb in either device, host, or otg configuration. 7.6.3.1 usb device controller the usb device controller enables 12 mbit/s data exchange with a usb host controller. it consists of register interface, serial interface engine, endpoint buffer memory and dma controller. the serial interface engine decodes the usb data stream and writes data to the appropriate end point buffer memory. the status of a completed usb transfer or error
lpc3220_30_40_50 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 2.1 ? 24 june 2014 32 of 80 nxp semiconductors lpc3220/30/40/50 16/32-bit arm microcontrollers condition is indicated via status registers. an interrupt is also generated if enabled. the dma controller when enabled transfers data between the endpoint buffer and the usb ram. features ? fully compliant with usb 2.0 full-speed specification . ? supports 32 physical (16 logical) endpoints. ? supports control, bulk, interrupt and isochronous endpoints. ? scalable realization of endpoints at run time. ? endpoint maximum packet size selection (up to usb maximum specification) by software at run time. ? ram message buffer size based on endpoint realization and maximum packet size. ? supports bus-powere d capability with low suspend current. ? supports dma transfer on all non-control endpoints. ? one duplex dma channel serves all endpoints. ? allows dynamic switching betwee n cpu controlled and dma modes. ? double buffer implementation for bulk and isochronous endpoints. 7.6.3.2 usb host controller the host controller enables data exchange with various usb devices attached to the bus. it consists of register interf ace, serial interface engine and dma controller. the register interface complies to the ohci specification . features ? ohci compliant. ? ohci specifies the operation and interface of the usb host controller and software driver. ? the host controller has four usb states visible to the software driver: ? usboperational: process lists and generate sof tokens. ? usbreset: forces reset signaling on the bus, sof disabled. ? usbsuspend: monitor usb for wake-up activity. ? usbresume: forces resume signaling on the bus. ? hcca register points to interrupt and isochronous descriptors list. ? controlheaded and bulkheaded registers po int to control and bu lk descriptors list. 7.6.3.3 usb otg controller usb otg (on-the-go) is a supplement to the usb 2.0 specification that augments the capability of existing mobile devices and usb peripherals by adding host functionality for connection to usb peripherals. features ? fully compliant with on-the-go supplement to the usb specification 2.0 revision 1.0 .
lpc3220_30_40_50 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 2.1 ? 24 june 2014 33 of 80 nxp semiconductors lpc3220/30/40/50 16/32-bit arm microcontrollers ? supports host negotiation protocol (hnp) and session request protocol (srp) for dual-role devices under software control. hnp is partially impl emented in hardware. ? provides programmable timers required for hnp and srp. ? supports slave mode operation through ahb slave interface. ? supports the otg atx from nxp (isp 1302) or any external cea-2011otg specification compliant atx. 7.6.4 lcd controller the lcd controller provides all of the necessary control signals to interface directly to a variety of color and monochrome lcd panels. both stn (single and dual panel) and tft panels can be operated. the display resolution is selectable and can be up to 1024 ? 768 pixels. several color modes are provided, up to a 24-bit true-color non-palettized mode. an on-chip 512-byte color palette allows reducing bus utilizati on (i.e. memory size of the displayed data) while still supporti ng a large number of colors. the lcd interface includes its own dma controlle r to allow it to operate independently of the cpu and other system functions. a built-in fifo acts as a buffer for display data, providing flexibility for system timing. hardware cursor su pport can furthe r reduce the amount of cpu time needed to operate the display. 7.6.4.1 features ? ahb bus master interface to access frame buffer. ? setup and control via a separate ahb slave interface. ? dual 16-deep programmable 64-bit wide fifos for buffering incoming display data. ? supports single and dual-panel monochrome super twisted nematic (stn) displays with 4-bit or 8-bit interfaces. ? supports single and dual-panel color stn displays. ? supports thin film transi stor (tft) color displays. ? programmable display resolution including, but not limited to: 320 ? 200, 320 ? 240, 640 ? 200, 640 ? 240, 640 ? 480, 800 ? 600, and 1024 ? 768. ? hardware cursor support for single-panel displays. ? 15 gray-level monochrome, 3375 color stn, and 32 k color palettized tft support. ? 1, 2, or 4 bits-per-pixel (bpp) palettized displays for monochrome stn. ? 1, 2, 4, or 8 bpp palettized color displays for color stn and tft. ? 16 bpp true-color non-palettized, for color stn and tft. ? 24 bpp true-color non-palettized, for color tft. ? programmable timing for different display panels. ? 256 entry, 16-bit palette ram, arranged as a 128 ? 32 bit ram. ? frame, line, and pixel clock signals. ? ac bias signal for stn, data enable signal for tft panels. ? supports little and big-endian, and windows ce data formats. ? lcd panel clock may be generated from the peripheral clock or from a clock input pin.
lpc3220_30_40_50 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 2.1 ? 24 june 2014 34 of 80 nxp semiconductors lpc3220/30/40/50 16/32-bit arm microcontrollers 7.7 system functions to enhance the performance of the lpc3220/30/40/50 incorporates the following system functions, an interrupt controller (intc), a watchdog timer, a millisecond timer, and several power control features. these functions are described in the following sections 7.7.1 interrupt controller the interrupt controller is comprised of three basic interrupt controller blocks, supporting a total of 73 interrupt sources. each interrupt source can be individually enabled/disabled and configured for high or low level triggering, or rising or falling edge triggering. each interrupt may also be steered to either the fiq or irq input of the arm9. raw interrupt status and masked interrupt status register s allow versatile condition evaluation. in addition to peripheral functions, each of th e six general purpose i nput/output pins and 12 of the 22 general purpose input pins are connected directly to the interrupt controller. 7.7.2 watchdog timer the watchdog timer block is clocked by the ma in peripheral clock, which clocks a 32-bit counter. a match register is compared to the timer. when configured for watchdog functionality, a match drives the match out put low. the match output is gated with an enable signal that gives the op portunity to generate two type of reset signal: one that only resets chip internally, and another that goes through a programmable pulse generator before it goes to the external pin resout and to the internal chip reset. 7.7.2.1 features ? programmable 32-bit timer. ? internally resets the device if not periodically reloaded. ? flag to indicate that a watchdog reset has occurred. ? programmable watchdog pulse output on resout pin. ? can be used as a standard timer if watchdog is not used. ? pause control to stop counting when core is in debug state. 7.7.3 millisecond timer the millisecond timer is clocked by 32 khz rt c clock, so a prescaler is not needed to obtain a lowe r count rate. the millisecond timer includes three match registers th at are compared to the timer/counter value. a match can generate an interrupt and the cause the timer/counter either continue to run, stop, or be reset. 7.7.3.1 features ? 32-bit timer/counter, running from the 32 khz rtc clock. ? counter or timer operation. ? three 32-bit match registers that allow: ? continuous operation with optional interrupt generation on match. ? stop timer on match with optional interrupt generation. ? reset timer on match with optional interrupt generation. ? pause control to stop counting when core is in debug state.
lpc3220_30_40_50 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 2.1 ? 24 june 2014 35 of 80 nxp semiconductors lpc3220/30/40/50 16/32-bit arm microcontrollers 7.7.4 clocking and power control features 7.7.4.1 clocking clocking in the lpc3220/30/40/50 is designed to be versatile, so that system and peripheral requirements may be met, while allowing optimization of power consumption. clocks to most functions may be turned off if not needed and some peripherals do this automatically. the lpc3220/30/40/50 supports three operation al modes, two of which are specifically designed to reduce power consumption. the modes are: run mode, direct run mode, and stop mode.these three operational modes give control over processing speed and power consumption. in addition, clock rates to different functional blocks may be changed by switching clock sources, changi ng pll values, or altering clock divider configurations. this allows a trade-off of power versus processing speed based on application requirements. 7.7.4.2 crystal oscillator the main oscillator is the basis for the cl ocks most chip func tions use by default. optionally, many functions can be clocked inst ead by the output of a pll (with a fixed 397x rate multiplication) whic h runs from the rtc oscillato r. in this mode, the main oscillator may be turned off un less the usb interface is enabl ed. if a sysclk frequency other than 13 mhz is required in the applicatio n, or if the usb block is not used, the main oscillator may be used wi th a frequency of between 1 mhz and 20 mhz. 7.7.4.3 plls the lpc3220/30/40/50 includes three plls: the 397x pll allows boosting the rtc frequency to 13.008896 mhz for use as the pr imary system clock. the usb pll provides the 48 mhz clock required by the usb block, and the hclk pll provides the basis for the cpu clock, the ahb bus clock, and the main peripheral clock. the 397x pll multiplies the 32768 hz rtc clock by 397 to obtain a 13.008896 mhz clock. the 397x pll is designed for low power operation and low jitter. this pll requires an external rc loop filter for proper operation. the hclk pll accepts an input cl ock from either the main osc illator or the output of the 397x pll. the usb pll only accepts an i nput clock from the main oscillator.the usb input clock runs through a divide-by-n pr e-divider before entering the usb pll. the input to the hclk and usb plls may init ially be divided down by a pre-divider value ?n?, which may have the values 1, 2, 3, or 4. this pre-divider can allo w a greater number of possibilities for the output freq uency. following the pll input divider is the pll multiplier. this can multiply the pre-divider output by a value ?m?, in the range of 1 through 256. the resulting frequency must be in the range of 156 mhz to 320 mhz. the multiplier works by dividing the output of a curren t controlled oscillator (cco) by the value of m, then using a phase detector to compare the divided cco output to the pre-divider output. the error value is used to adjust the cco frequency. at the pll output, there is a post-divider that can be used to bring the cco frequency down to the desired pll output frequency. the post-divider value can divide the cco output by 1, 2, 4, 8, or 16. the post-divid er can also be bypassed, allowing the pll cco
lpc3220_30_40_50 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 2.1 ? 24 june 2014 36 of 80 nxp semiconductors lpc3220/30/40/50 16/32-bit arm microcontrollers output to be used directly. the maximum pll output frequency supported by the cpu is 266 mhz. the only output frequency supported by the usb pll is 48 mhz, and the clock has strict requirements for nominal frequency (500 ppm) and jitter (500 ps). 7.7.4.4 power control modes the lpc3220/30/40/50 supports three operation al modes, two of which are specifically designed to reduce power consumption. the modes are: run mode, direct run mode, and stop mode. run mode is the normal operating mode for a pplications that require the cpu, ahb bus, or any peripheral function other than the usb block to run fa ster than the main oscillator frequency. in run mode, the cpu can run at up to 266 mhz and the ahb bus can run at up to 133 mhz. direct run mode allows reducing the cpu and ahb bus rates in order to save power. direct run mode can also be the normal opera ting mode for applications that do not require the cpu, ahb bus, or any peripheral function other than the usb block to run faster than the main oscillato r frequency. direct run mode is the de fault mode following chip reset. stop mode causes all cpu and ahb operation to cease, and stops clocks to peripherals other than the usb block. 7.7.4.5 reset reset is accomplished by an active low signal on the reset input pin. a reset pulse with a minimum width of 10 main oscillator clocks af ter the oscillator is stable is required to guarantee a valid chip rese t. at power-up, 10 milliseconds should be allowed for the oscillator to start up and stabilize after v dd reaches operational voltage. an internal reset with a minimum duration of 10 clock pulses will also be app lied if the watchdog timer generates an internal device reset. the reset pin is located in the rtc power do main. this means that the rtc power must be present for an external reset to have any effect. the rtc power domain nominally runs from 1.2 v, but the reset pin can be driven as high as 1.95 v. 7.8 communication peripheral interfaces in addition to the ethernet mac and usb interfaces there are many more serial communication peripheral interfaces availabl e on the lpc3220/30/40/50. here is a list of the serial communica tion interfaces: ? seven uarts; four standard uarts and three high-speed uarts ? two spi serial i/o controllers ? two ssp serial i/o controllers ? two i 2 c serial i/o controllers ? two i 2 s audio controllers a short functional description of each of th ese peripherals is provided in the following sections.
lpc3220_30_40_50 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 2.1 ? 24 june 2014 37 of 80 nxp semiconductors lpc3220/30/40/50 16/32-bit arm microcontrollers 7.8.1 uarts the lpc3220/30/40/50 contains seven uarts. four are standard uarts, and three are high-speed uarts. 7.8.1.1 standard uarts the four standard uarts are compatible with the ins16cx50. these uarts support rates up to 460800 bit/s from a 13 mhz peripheral clock. features ? each standard uart has 64 byte receive and transmit fifos. ? receiver fifo trigger points at 16, 32, 48, and 60 bytes. ? transmitter fifo trigger points at 0, 4, 8, and 16 bytes. ? register locations conform to the ?550? industry standard. ? each standard uart has a fractional rate pre-divider and an internal baud rate generator. ? the standard uarts support three clocking modes: on, off, and auto-clock. the auto-clock mode shuts off the clo ck to the uart when it is idle. ? uart 6 includes an irda mode to support infrared communication. ? the standard uarts are designed to support data rates of (2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400, 460800) bit/s. ? each uart includes an internal loopback mode. 7.8.1.2 high-speed uarts the three high-speed uarts are designed to support rates up to 921600 bit/s from a 13 mhz peripheral clock for on-board communi cation in low noise conditions. this is accomplished by changing the over sampling from 16 ? to 14 ? and altering the rate generation logic. features ? each high-speed uart has 64-byte receive and transmit fifos. ? receiver fifo trigger points at 1, 4, 8, 16, 32, and 48 b. ? transmitter fifo trigger points at 0, 4, and 8 b. ? each high-speed uart has an internal baud rate generator. ? the high-speed uarts are designed to su pport data rates of (2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600) bit/s. ? the three high speed uarts only support (8n1) 8-bit data word length, 1-stop bit, no parity, and no flow control as a the communications protocol. ? each uart includes an internal loopback mode. 7.8.2 spi serial i/o controller the lpc3220/30/40/50 has two serial peripher al interfaces (spi). the spi is a 3-wire serial interface that is able to interface with a large range of serial peripheral or memory devices (spi mode 0 to 3 compatible slave devices).
lpc3220_30_40_50 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 2.1 ? 24 june 2014 38 of 80 nxp semiconductors lpc3220/30/40/50 16/32-bit arm microcontrollers only a single master and a single slave can communicate on the interface during a given data transfer. during a data transfer the master always sends a byte of data to the slave, and the slave always sends a byte of data to the master. the spi implementation on the lpc3220/30/40/50 does not support operation as a slave. 7.8.2.1 features ? supports slaves compatible with spi modes 0 to 3. ? half duplex synchronous transfers. ? dma support for data transmit and receive. ? 1-bit to 16-bit word length. ? choice of lsb or msb first data transmission. ? 64 ? 16-bit input or output fifo. ? bit rates up to 52 mbit/s. ? busy input function. ? dma time out interrupt to allow detection of end of reception when using dma. ? timed interrupt to facilitat e emptying the fifo at the end of a transmission. ? spi clock and data pins may be used as g eneral purpose pins if the spi is not used. ? slave selects can be supported using gpo or gpio pins 7.8.3 ssp serial i/o controller the lpc3220/30/40/50 contains two ssp cont rollers. the ssp controller is capable of operation on a spi, 4-wire ssi, or microwire bus . it can interact with multiple masters and slaves on the bus. only a single master and a single slave can communicate on the bus during a given data transfer. the ssp supports full duplex transfers, wi th frames of 4 bits to 16 bits of data flowing from the master to the slave and from the slave to the master. in practice, often only one of these data flows carries meaningful data. 7.8.3.1 features ? compatible with motorola spi , 4-wire ti ssi, and national semiconductor microwire buses ? synchronous serial communication ? master or slave operation ? 8-frame fifos for both transmit and receive ? 4-bit to 16-bit frame ? maximum spi bus data bit rate of 1 2 (master mode) and 1 2 (slave mode) of the input clock rate ? dma transfers supported by gpdma 7.8.4 i 2 c-bus serial i/o controller there are two i 2 c-bus interfaces in the lpc32x0 family of controllers. these i 2 c blocks can be configured as a master, multi-master or slave supporting up to 400 khz. the i 2 c blocks also support 7 or 10 bit addressing. ea ch has a four word fifo for both transmit and receive. an interrupt signal is available from each block.
lpc3220_30_40_50 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 2.1 ? 24 june 2014 39 of 80 nxp semiconductors lpc3220/30/40/50 16/32-bit arm microcontrollers there is a separate slave transmit fifo. the slave transmit fifo (txs) and its level are only available when the controller is configured as a master/slave device and is operating in a multi-master environment. separate tx fifos are needed in a multi-master because a controller might have a message queued for transmission when an external master addresses it to be come a slave-transmitter, a second source of data is needed. note that the i 2 c clock must be enabled in the i2cclk_ctrl register before using the i 2 c. the i 2 c clock can be disabled between communi cations, if used as a single master i 2 c-bus interface, software has full control of when i 2 c communication is taking place on the bus. 7.8.4.1 features ? the two i 2 c-bus blocks are standard i 2 c-bus compliant interfaces that may be used in single-master, multi-master or slave modes. ? programmable clock to allow adjustment of i 2 c-bus transfer rates. ? bidirectional data transfer. ? serial clock synchronization allows devices with different bit rates to communicate via one serial bus. ? serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer. 7.8.5 i 2 s-bus audio controller the i 2 s-bus provides a standard communication interface for digital audio applications the i 2 s-bus specification defines a 3-wire serial bus using one data line, one clock line, and one word select signal. each i 2 s connection can act as a master or a slave. the master connection determines the frequency of the clock line and all other slaves are driven by this clock source. the two i 2 s-bus interfaces on the lpc3220/30/40/50 provides a separate transmit and receive channel, pr oviding a total of two transmit channels and two receive channels. each i 2 s channel supports monaural or stereo formatted data. 7.8.5.1 features ? the interface has separate input/output chan nels each of which can operate in master or slave mode. ? capable of handling 8-bit, 16-bit, and 32-bit word sizes. ? mono and stereo audio data supported. ? supports standard sampling frequencies (8 khz, 11.025 khz, 16 khz, 22.05 khz, 32 khz, 44.1 khz, 48 khz, 96 khz). ? word select period can be configured in master mode (separately for i 2 s input and output). ? two eight-word fifo data buffers are provided, one for transmit and one for receive. ? generates interrupt requests when buffer levels cross a programmable boundary. ? two dma requests, controlled by programma ble buffer levels. these are connected to the gpdma block. ? controls include reset, stop, and mute options separately for i 2 s input and i 2 s output.
lpc3220_30_40_50 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 2.1 ? 24 june 2014 40 of 80 nxp semiconductors lpc3220/30/40/50 16/32-bit arm microcontrollers 7.9 other peripherals in addition to the communication peripherals there are many general purpose peripherals available in the lpc3220/30/40/50. here is a list of the general purpose peripherals. ? gpi/o ? keyboard scanner ? touch screen controller and 10-bit analog-to-digital-converter ? real-time clock ? high-speed timer ? four general purpose 32-bit timer/external event counters ? two simple pwms ? one motor control pwm a short functional description of each of th ese peripherals is provided in the following sections. 7.9.1 general purpose parallel i/o some device pins that are not dedicated to a specific peripheral function have been designed to be general purpose inputs, outputs, or input/outputs. also, some pins may be configured either as a specific peripheral function or a general purpose input, output, or input/output. a total of 51 pins can potentially be used as general purpose input/outputs, 24 as general purpose outputs, and 22 as general purpose inputs. gpio pins may be dynamically configured as inputs or outputs. separate registers allow setting or clearing any number of gpio and gpo outputs controlled by that register simultaneously. the value of the output register for standard gpios and gpo pins may be read back, as well as the current actual state of the port pins. in addition to gpio pins on port 0, port 1, and port 2, there are 22 gpi, 24 gpo, and six gpio pins. when the sdram bus is configured for 16 data bits, 13 of the remaining sdram data pins may be used as gpios. 7.9.1.1 features ? bit-level set and clear registers allow a single instruction set or clear of any number of bits in one port. ? a single register selects direction for pins that support both input and output modes. ? direction control of individual bits. ? for input/output pins, both the programmed output state and the actual pin state can be read. ? there are a total of 12 general purpose inputs, 24 general purpose outputs, and six general purpose input/outputs. ? additionally, 13 sdram data lines may be used as gpios if a 16-bit sdram interface is used (rather than a 32-bit interface).
lpc3220_30_40_50 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 2.1 ? 24 june 2014 41 of 80 nxp semiconductors lpc3220/30/40/50 16/32-bit arm microcontrollers 7.9.2 keyboard scanner the keyboard scanner function can automatically scan a keyboard of up to 64 keys in an 8 ? 8 matrix. in operation, the keyboard scanner?s internal state machine will normally be in an idle state, with all key_rown pins se t high, waiting for a ch ange in the column inputs to indicate that one or more keys have been pressed. when a keypress is detected, the matrix is scanned by setting one output pin high at a time and reading the column inputs. after de-bouncing, the keypad state is stored and an interrupt is generated. the keypad is then continuously scanned waiting for ?extra key pressed? or ?key released?. any new keypad state is scanned and stored into the matrix registers followed by a new interrupt request to the interrupt controller. it is possible to detect and separate up to 64 multiple keys pressed. 7.9.2.1 features ? supports up to 64 keys in 8 ? 8 matrix. ? programmable de-bounce period. ? a key press can wake up the cpu from stop mode. 7.9.3 touch screen controller and 10-bit adc the lpc3220/30/40/50 microcontrollers includes touch screen controller (tsc) hardware, which automatically measures and determines the x and y coordinates where a touch screen is pressed. in addition, t he tsc can measure an analog input signal on the aux_in pin. optionally, the tsc can operate as an anal og-to-digital converter (adc). the adc supports three channels and uses 10-bit successive approximation to produce results with a resolution of 10 bits in 11 clock cycles. the analog portion of the adc has its own power supply to enhance the low noise characteristics of the converter. this voltage is only supplied internally when the core has voltage. however, the adc blo ck is not affected by any difference in ramp-up time for vdd_ad and vdd_core voltage supplies. 7.9.3.1 features ? measurement range of 0 v to vdd_ad (nominally 3.3 v). ? low-noise adc. ? 10-bit resolution. ? three input channels. ? uses 32 khz rtc clock or peripheral clock. 7.9.4 real-time clock (rtc) and battery ram the rtc runs at 32768 hz using a very low power oscillator. the rtc counts seconds and can generate alarm interrupts that can wake up the device from stop mode. the rtc clock can also clock the 397x pll, the millisec ond timer, the adc, the keyboard scanner and the pwms. the rtc up-counter value repr esents a number of seconds elapsed since second 0, which is an appl ication determined time. the rtc counter will reach maximum value after about 136 years. the rtc down-counter is initiated with all ones.
lpc3220_30_40_50 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 2.1 ? 24 june 2014 42 of 80 nxp semiconductors lpc3220/30/40/50 16/32-bit arm microcontrollers two 32-bit match registers are readable and writable by the processor. a match will result in an interrupt provided that the interrupt is enabled. the onsw output pin can also be triggered by a match event and cause an external power supply to turn on all of the operating voltages, as a way to startup after power has been removed. the rtc block is implemented in a separate voltage domain. the block is supplied via a separate supply pin from a battery or other power source. the rtc block also contains 32 words (128 byte s) of very low voltage sram. this sram is able to hold its contents down to the minimum rtc operating voltage. 7.9.4.1 features ? measures the passage of time in seconds. ? 32-bit up and down seconds counters. ? ultra-low power design to support battery powered systems. ? dedicated 32 khz oscillator. ? an output pin is included to assist in waking up when the chip has had power removed to all functions except the rtc. ? two 32-bit match registers with interrupt option. ? 32 words (128 bytes) of very low voltage sram. ? the rtc and battery ram power have an independent power domain and dedicated supply pins, which can be powered from a battery or power supply. remark: the lpc3220/30/40/50 will run at voltages down to 0.9 v at frequencies below 14 mhz. however, the arm core cannot ac cess the rtc registers and battery ram when the core supply voltage is at 0.9 v and the rtc supply is at 1.2 v. 7.9.5 enhanced 32-bit timers/external event counters the lpc3220/30/40/50 includes six 32-bit timer/counters. the timer/counter is designed to count cycles of the system derive d clock or an externally-supplied clock. it can optionally generate interrupts or perf orm other actions at specified timer values, based on four match registers. the timer/counter also includes four capture inputs to trap the timer value when an input signal transitions, optionally generating an interrupt. 7.9.5.1 features ? a 32-bit timer/counter with a programmable 32-bit pre-scaler. ? counter or timer operation. ? up to four 32-bit capture channels per time r, that can take a snapshot of the timer value when an input signal transitions. a capture event may also optionally generate an interrupt. ? four 32-bit match registers that allow: ? continuous operation with optional interrupt generation on match ? stop timer on match with optional interrupt generation ? reset timer on match with op tional interrupt generation ? up to four external outputs corresponding to match registers, with the following capabilities:
lpc3220_30_40_50 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 2.1 ? 24 june 2014 43 of 80 nxp semiconductors lpc3220/30/40/50 16/32-bit arm microcontrollers ? set low on match ? set high on match ? toggle on match ? do nothing on match 7.9.6 high-speed timer the high-speed timer block is clocked by the main peripheral clock. the clock is first divided down in a 16-bit programmable pre-scale counter which clocks a 32-bit timer/counter. the high-speed timer includes three ma tch registers that are compared to the timer/counter value. a match can generate an interrupt and cause the timer/counter to either continue to run, stop, or be reset. the high-speed timer also includes two capture registers that can take a snapshot of th e timer/counter value when an input signal transitions. a capture event may also generate an interrupt. 7.9.6.1 features ? 32-bit timer/counter with programmable 16-bit pre-scaler. ? counter or timer operation. ? two 32-bit capture registers. ? three 32-bit match registers that allow: ? continuous operation with optional interrupt generation on match. ? stop timer on match with optional interrupt generation. ? reset timer on match with optional interrupt generation. ? pause control to stop counting when core is in debug state. 7.9.7 pulse width modulators (pwms) the lpc3220/30/40/50 provides two simple pwms . they are clocked separately by either the main peripheral clock or the 32 khz rtc clock. both pwms have a duty cycle programmable in 255 steps. 7.9.7.1 features ? clocked by the main peripheral clock or the 32 khz rtc clock. ? programmable 4-bit pre-scaler. ? duty cycle programmable in 255 steps. ? output frequency up to 50 khz when using a 13 mhz peripheral clock. 7.9.8 motor control pulse width modulator the motor control pwm (mcpwm) provides a set of features for three-phase ac and dc motor control applications in a single peripheral. the mcpwm can also be configured for use in other generalized timing, counti ng, capture, and compare applications. 7.9.8.1 features ? 32-bit timer ? 32-bit period register
lpc3220_30_40_50 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 2.1 ? 24 june 2014 44 of 80 nxp semiconductors lpc3220/30/40/50 16/32-bit arm microcontrollers ? 32-bit pulse-width (match) register ? 10-bit dead-time register and an a ssociated 10-bit dead-time counter ? 32-bit capture register ? two pwm (match) outputs (pins mcoa0/1/2 and mcob0/1/2) with opposite polarities ? period interrupt, pulse-width interrupt, and capture interrupt 8. basic architecture the lpc3220/30/40/50 is a general purpos e arm926ej-s 32-bit microprocessor with a 32 kb instruction cache and a 32 kb data cache. the microcontroller offers high performance and very low power consumption. the arm architecture is based on risc principles, which results in t he instruction set and related decode mechanism being much simpler than equivalent micro programmed ci scs. this simplicity results in a high instruction throughput and impressive real-time interrupt response from a small and cost-effective processor core. the arm926ej-s core employs a 5-stage pipeline so processing and memory system accesses can occur continuously. at any one point in time, several operations are in progress: subsequent instructio n fetch, next instruction de code, instruction execution, memory access, and write-back. the combination of architectural enhancements gives the arm9 about 30 % better performance than an arm7 running at the same clock rate: ? approximately 1.3 clocks per instruction fo r the arm926ej-s compared to 1.9 clocks per instruction for arm7tdmi. ? approximately 1.1 dhrystone mips/mhz for the arm926ej-s compared to 0.9 dhrystone mips/mhz for arm7tdmi. the arm926ej-s processor also employs an operational state known as thumb, which makes it ideally suited to high-volume applications with memory restrictions, or applications where code density is an issue. the key idea behind thumb state is the use of a super-reduced instruction set. essentially, the arm926ej-s processor core has two instruction sets: 1. the standard 32-bit arm set 2. the 16-bit thumb set the thumb set?s smaller 16-bit in struction length allows it to approach twice the density of standard arm code while retaining many of arm?s 32-bit performance advantage over a traditional 16-bit processor using 16-bit regist ers. this is possible because thumb code operates using the same 32-bit register set as arm code. thumb code size is up to 65 % smaller than arm code size, and 160 % of the performance of an equivalent arm processor connected to a 16-bit memory system. additionally, the arm926ej-s core includes enhanced dsp instructions and multip lier, as well as an enhanced 32-bit mac block.
lpc3220_30_40_50 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 2.1 ? 24 june 2014 45 of 80 nxp semiconductors lpc3220/30/40/50 16/32-bit arm microcontrollers 9. limiting values [1] the following applies to table 7 : a) this product includes circuitry specif ically designed for the protection of its in ternal devices from the damaging effects of excessive static charge. nonetheless, it is sugges ted that conventional precautions be tak en to avoid applying greater than the rated maximum. b) parameters are valid over operating te mperature range unless otherwise specifi ed. all voltages are with respect to v ss unless otherwise noted. [2] core, pll, oscillator, and rtc supplies; applies to pins vdd_core, vdd_corefxd, vdd_osc, vdd_pll397, vdd_pllhclk, vdd_pllusb, vdd_rtc, vdd_rtccore, and vdd_rtcosc. [3] i/o pad supply; applies to domains vdd_emc. [4] applies to vdd_ad pins. [5] applies to pins in the following domains vdd_ioa, vdd_iob, vdd_ioc, and vdd_iod. [6] including voltage on outputs in 3-state mode. [7] based on package heat transfer, not device power consumption. calculated package thermal resistance (theta ja ): 35.766 ? c/w (with jedec test board and 0 m/s airflow, ? 15 % accuracy). [8] human body model: equivalent to dischar ging a 100 pf capacitor through a 1.5 k ? series resistor. [9] charge device model per aec-q100-011. table 7. limiting values in accordance with the absolute ma ximum rating system (iec 60134). [1] symbol parameter conditions notes min max unit v dd(1v2) supply voltage (1.2 v) [2] ? 0.5 +1.4 v v dd(emc) external memory controller supply voltage [3] ? 0.5 +4.6 v v dda(3v3) analog supply voltage (3.3 v) [4] ? 0.5 +4.6 v v dd(io) input/output supply voltage [5] ? 0.5 +4.6 v v ia analog input voltage ? 0.5 +4.6 v v i input voltage 1.8 v pins [6] ? 0.5 +2.4 v 3.3 v pins [6] ? 0.5 +4.6 v i dd supply current per supply pin - 100 ma i ss ground current per ground pin - 100 ma t stg storage temperature ? 65 +150 ?c p tot(pack) total power dissipation (per package) max. junction temp 125 ?c max. ambient temp 85 ?c [7] -1.12w v esd electrostatic discharge voltage hbm [8] - 2500 v cdm [9] - 1000 v
lpc3220_30_40_50 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 2.1 ? 24 june 2014 46 of 80 nxp semiconductors lpc3220/30/40/50 16/32-bit arm microcontrollers 10. static characteristics table 8. static characteristics t amb = ? 40 ? c to +85 ? c, unless otherwise specified. symbol parameter conditions min typ [1] max unit v dd(1v2) supply voltage (1.2 v) core supply voltage for full performance; 266 mhz (see figure 4 ); vdd_core supply domain [2] 1.31 1.35 1.39 v core supply voltage for normal performance; 208 mhz (see figure 4 ); vdd_core supply domain [2] 1.1 1.2 1.39 v core supply voltage for reduced power; up to 14 mhz cpu; vdd_core supply domain [2] 0.9 - 1.39 v rtc supply voltage; vdd_rtc supply domain [3] 0.9 - 1.39 v pll and oscillator supply voltage [4] 1.1 1.2 1.39 v v dd(emc) external memory controller supply voltage in 1.8 v range [5] 1.7 1.8 1.95 v in 2.5 v range [6] 2.3 2.5 2.7 v in 3.3 v range [7] 2.7 3.3 3.6 v v dd(io) input/output supply voltage vdd_ioa, vdd_iob, and vdd_iod supply domain in 1.8 v range 1.7 1.8 1.95 v in 3.3 v range 2.7 3.3 3.6 v vdd_ioc supply domain in 1.8 v range 1.7 1.8 1.95 v in 3.3 v range 2.3 3.3 3.6 v v dda(3v3) analog supply voltage (3.3 v) applies to pins in vdd_ad power domain 2.7 3.3 3.6 v
lpc3220_30_40_50 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 2.1 ? 24 june 2014 47 of 80 nxp semiconductors lpc3220/30/40/50 16/32-bit arm microcontrollers power consumption in run, direct run, and stop modes i dd(run) run mode supply current t amb =25 ?c; code while(1){} executed from iram; all peripherals enabled i-cache/d-cache, mmu enabled; cpu clock = 208 mhz; vdd_core = 1.2 v - 150 - ma i-cache/d-cache, mmu enabled; cpu clock = 266 mhz; vdd_core = 1.35 v - 218 - ma i-cache/d-cache, mmu disabled; cpu clock = 208 mhz; vdd_core = 1.2 v -7 8-m a i-cache/d-cache, mmu disabled; cpu clock = 266 mhz; vdd_core = 1.35 v - 111 - ma i dd(drun) direct run mode supply current t amb =25 ? c; cpu clock = 13 mhz; code while(1){} executed from iram; all peripherals disabled i-cache/d-cache, mmu enabled; vdd_core = 1.2 v -7.8-ma i-cache/d-cache, mmu enabled; vdd_core = 0.9 v -5.6-ma i-cache/d-cache, mmu disabled; vdd_core = 1.2 v -5-ma i-cache/d-cache, mmu disabled; vdd_core = 0.9 v -3.5-ma i dd(stop) stop mode supply current t amb =25 ? c; cpu clock stopped internally; all peripherals disabled vdd_core = 1.2 v - 400 - ? a vdd_core = 0.9 v - 400 - ? a table 8. static characteristics ?continued t amb = ? ? ? symbol parameter conditions min typ [1] max unit
lpc3220_30_40_50 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 2.1 ? 24 june 2014 48 of 80 nxp semiconductors lpc3220/30/40/50 16/32-bit arm microcontrollers i dd(rtc) rtc supply current normal operation; vdd_rtc = vdd_rtccore = vdd_rtcosc = 1.2 v; t amb =25 ?c [8] -1 3- ? a rtc back up operation; rev ?-? silicon [9] -3 0- ? a rev ?a? silicon [9] -4- i dd supply current for hclk; pll output frequency = 266 mhz; vdd_pllhclk = 1.2 v -2-m a for usb; vdd_pllusb = 1.2 v -2-m a for adc; interrupt driven loop converting adin[2:0]; vdd_ad = 3.3 v - ? 1- ma input pins and i/o pins configured as input v i input voltage [10] [12] 0-v dd(io) v v ih high-level input voltage 1.8 v inputs 0.7 ? v dd(io) -- v 3.3 v inputs 0.7 ? v dd(io) -- v v il low-level input voltage 1.8 v inputs - - 0.3 ? v dd(io) v 3.3 v inputs - - 0.3 ? v dd(io) v v hys hysteresis voltage 1.8 v inputs 0.1 ? v dd(io) -- v 3.3 v inputs 0.1 ? v dd(io) -- v i il low-level input current v i = 0 v; no pull-up - - 1 ? a i ih high-level input current v i = v dd(io) ; no pull-down [10] --1 ? a i latch i/o latch-up current ? (1.5v dd(io) ) < v i < (1.5v dd(io) ) [10] --1 0 0m a i pu pull-up current 1.8 v inputs with pull-up; v i = 0 v 61 22 2 ? a 3.3 v inputs with pull-up; v i = 0 v 25 50 80 ? a i pd pull-down current 1.8 v inputs with pull-down; v i = v dd(io) 51 22 2 ? a 3.3 v inputs with pull-down; v i = v dd(io) 25 50 85 ? a i i input current bus keeper inputs; v i = v dd --1 ? a v i = 0.67 ? v dd --5 5 ? a v i = 0.33 ? v dd --6 0 ? a v i = 0 v - - 1 ? a c i input capacitance excluding bonding pad capacitance --3.3pf table 8. static characteristics ?continued t amb = ? 40 ? c to +85 ? c, unless otherwise specified. symbol parameter conditions min typ [1] max unit
lpc3220_30_40_50 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 2.1 ? 24 june 2014 49 of 80 nxp semiconductors lpc3220/30/40/50 16/32-bit arm microcontrollers output pins and i/o pins configured as output v o output voltage [10] [11] [12] [13] 0-v dd(io) v v oh high-level output voltage 1.8 v outputs; i oh = ? 1 ma [14] v dd(io) ? 0.4 - - v 3.3 v outputs; i oh = ? 4 ma [14] v dd(io) ? 0.4 - - v v ol low-level output voltage 1.8 v outputs; i ol = 4 ma [14] --0 . 4v 3.3 v outputs; i ol = 4 ma [14] --0 . 4v i oh high-level output current v dd(io) = 1.8 v; v oh = v dd(io) ? 0.4 v [10] [14] ? 3.3 - - ma v dd(io) = 3.3 v; v oh = v dd(io) ? 0.4 v ? 6.5 - - ma i ol low-level output current v dd(io) = 1.8 v; v ol = 0.4 v [10] [14] 1.5 - - ma v dd(io) = 3.3 v; v ol = 0.4 v 3 - - ma i oz off-state output current v o = 0 v; v o =v dd(io) ; no pull-up/down [10] --1 ? a i ohs high-level short-circuit output current v dd(io) = 1.8 v; v oh = 0 v [15] --6 6m a v dd(io) = 3.3 v; v oh = 0 v - - 183 ma i ols low-level short-circuit output current v dd(io) = 1.8 v; v ol = v dd(io) [10] [15] --3 4m a v dd(io) = 3.3 v; v ol = v dd(io) --1 0 5m a z o output impedance v dd(io) = 1.8 v 40 - 60 ? v dd(io) = 3.3 v 40 - 60 ? emc pins v i input voltage [12] 0-v dd(emc) v v ih high-level input volt age 1.8 v inputs 0.7 ? v dd(emc) -- v 3.3 v inputs 0.7 ? v dd(emc) -- v v il low-level input voltage 1.8 v inputs - - 0.3 ? v dd(emc) v 3.3 v inputs - - 0.3 ? v dd(emc) v v hys hysteresis voltage 1.8 v inputs 0.4 - 0.6 v 3.3 v inputs 0.55 - 0.85 v i il low-level input current v i = 0 v; no pull-up - - 0.3 ? a i ih high-level input current v i = v dd(emc) ; no pull-down - - 0.3 ? a i latch i/o latch-up current ? (1.5v dd(emc) ) < v i < (1.5v dd(emc) ) --100ma i pu pull-up current 1.8 v inputs with pull-up; v i = 0 34 62 107 ? a 3.3 v inputs with pull-up; v i = 0 97 169 271 ? a table 8. static characteristics ?continued t amb = ? 40 ? c to +85 ? c, unless otherwise specified. symbol parameter conditions min typ [1] max unit
lpc3220_30_40_50 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 2.1 ? 24 june 2014 50 of 80 nxp semiconductors lpc3220/30/40/50 16/32-bit arm microcontrollers i pd pull-down current 1.8 v inputs with pull-down; v i = v dd(emc) 23 51 93 ? a 3.3 v inputs with pull-down; v i = v dd(emc) 73 155 266 ? a c i input capacitance excluding bonding pad capacitance --2.1pf v o output voltage [11] [12] [13] 0-v dd(emc) v v oh high-level output voltage 1.8 v outputs; i oh = ? 1 ma [14] v dd(emc) ? 0.3 - - v 3.3 v outputs; i oh = ? 4 ma [14] v dd(emc) ? 0.3 - - v v ol low-level output voltage 1.8 v outputs; i ol = 4 ma [14] --0 . 3v 3.3 v outputs; i ol = 4 ma [14] --0 . 3v i oh high-level output current v dd(emc) = 1.8 v; v oh = v dd(emc) ? 0.4 v [14] ? 6-- ma v dd(emc) = 3.3 v; v oh = v dd(emc) ? 0.4 v ? 6-- m a i ol low-level output current v dd(emc) = 1.8 v; v ol = 0.4 v [14] 6-- m a v dd(emc) = 3.3 v; v ol = 0.4 v 6-- ma i oz off-state output current v o = 0 v; v o =v dd(emc) ; no pull-up/down --0.3 ? a i ohs high-level short-circuit output current v dd(emc) = 1.8 v; v oh = 0 v [15] -- ? 49 ma v dd(emc) = 3.3 v; v oh = 0 v - - ? 81 ma i ols low-level short-circuit output current v dd(emc) = 1.8 v; v ol = v dd(emc) [14] --4 9m a v dd(emc) = 3.3 v; v ol = v dd(emc) --8 6m a z o output impedance v dd(emc) = 1.8 v 35 40 58 ? v dd(emc) = 3.3 v 32 35 45 ? i 2 c pins v i input voltage [10] [12] 0-5 . 5v v ih high-level input voltage 1.8 v inputs 0.7 ? v dd(io) -- v 3.3 v inputs 0.7 ? v dd(io) -- v v il low-level input voltage 1.8 v inputs - - 0.3 ? v dd(io) v 3.3 v inputs - - 0.3 ? v dd(io) v i il low-level input current v i = 0 v; no pull-up - - 10 ? a i ih high-level input current v i = v dd(io) ; no pull-down [10] --1 0 ? a i latch i/o latch-up current ? (1.5v dd(io) ) < v i < (1.5v dd(io) ) [10] --1 0 0m a table 8. static characteristics ?continued t amb = ? 40 ? c to +85 ? c, unless otherwise specified. symbol parameter conditions min typ [1] max unit
lpc3220_30_40_50 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 2.1 ? 24 june 2014 51 of 80 nxp semiconductors lpc3220/30/40/50 16/32-bit arm microcontrollers c i input capacitance excluding bonding pad capacitance --1.6pf v ol low-level output voltage 1.8 v outputs; i ol = 4 ma [14] --0 . 4v 3.3 v outputs; i ol = 4 ma [14] --0 . 4v i ol low-level output current v dd(io) = 1.8 v; v ol = 0.4 v [10] [14] 3-- m a v dd(io) = 3.3 v; v ol = 0.4 v 3 - - ma i oz off-state output current v o = 0 v; v o =v dd(io) ; no pull-up/down [10] --1 0 ? a i ols low-level short-circuit output current v dd(io) = 1.8 v; v ol = v dd(io) [10] [15] --4 0m a v dd(io) = 3.3 v; v ol = v dd(io) --4 0m a onsw pin v o output voltage [10] [11] [12] [13] 0-v dd(1v2) v v oh high-level output voltage 1.2 v outputs; i oh = ? 1 ma [14] v dd(1v2) ? 0.4 - - v v ol low-level output voltage 1.2 v outputs; i ol = 4 ma [14] --0 . 4v i oh high-level output current v oh = v dd(1v2) ? 0.4 v [10] [14] ? 4-- ma i ol low-level output current v ol = 0.4 v [10] [14] 3-- m a i oz off-state output current v o = 0 v; v o =v dd(1v2) ; no pull-up/down [10] --1 . 5 ? a i ohs high-level short-circuit output current v dd(1v2) = 1.8 v; v oh = 0 v [15] -- ? 135 ma i ols low-level short-circuit output current v ol = v dd(1v2) [10] [15] --1 3 5m a z o output impedance v dd(1v2) = 1.2 v 40 - 60 ? oscillator input/output pins v i(xtal) crystal input voltage on pins rtcx_in and sysx_in ? 0.5 - +1.3 v v o(xtal) crystal output voltage on pins rtcx_out and sysx_out ? 0.5 - +1.3 v reset pin v i input voltage [10] [12] 0 - 1.95 v v ih high-level input volt age 1.2 v inputs 0.7 ? v dd(1v2) -- v v il low-level input voltage 1.2 v inputs - - 0.3 ? v dd(1v2) v i il low-level input current v i = 0 v; no pull-up - - 1 ? a table 8. static characteristics ?continued t amb = ? 40 ? c to +85 ? c, unless otherwise specified. symbol parameter conditions min typ [1] max unit
lpc3220_30_40_50 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 2.1 ? 24 june 2014 52 of 80 nxp semiconductors lpc3220/30/40/50 16/32-bit arm microcontrollers [1] typical ratings are not guaranteed. the va lues listed are at room temperature (25 ? c), nominal supply voltages. [2] applies to vdd_core pins. [3] applies to pins vdd_rtc, vdd_rtccore, and vdd_rtcosc. [4] applies to pins vdd_corefxd, vdd_os c, vdd_pll397, vdd_pllhclk, and vdd_pllusb. [5] applies when using 1.8 v mobile ddr or mobile sdr sdram. [6] applies when using 2.5 v ddr memory. [7] applies when using 3.3 v sdr sdram and sram. [8] specifies current on combined vdd_rtcx during normal chip operation: vdd_rtc, vdd_core, vdd_osc = 1.2 v and vdd_core, vdd_iox at typical voltage. [9] specifies current on combined vdd_rtcx during backup operation: vdd_rtc, vdd_core, vdd_osc = 1.2 v and all other vdd_x at 0 v. [10] referenced to the applicable v dd for the pin. [11] including voltage on outputs in 3-state mode. [12] the applicable v dd voltage for the pin must be present. [13] 3-state outputs go into 3-state mode when the applicable v dd voltage for the pin is grounded. [14] accounts for 100 mv voltage drop in all supply lines. [15] allowed as long as the current limit does not exceed the maximum current allowed by the device. i ih high-level input current v i = v dd ; no pull-down [10] --1 ? a i oz off-state output current v o = 0 v; v o =v dd ; no pull-up/down [10] --1 ? a i latch i/o latch-up current ? (1.5v dd ) < v i < (1.5v dd ) [10] --1 0 0m a table 8. static characteristics ?continued t amb = ? 40 ? c to +85 ? c, unless otherwise specified. symbol parameter conditions min typ [1] max unit
lpc3220_30_40_50 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 2.1 ? 24 june 2014 53 of 80 nxp semiconductors lpc3220/30/40/50 16/32-bit arm microcontrollers 10.1 minimum core voltage requirements figure 4 shows the minimum core supply voltage that should be applied for a given core frequency on pin vdd_core to ensure stable operation of the lpc3220/30/40/50. 10.2 power supply sequencing the lpc32x0 has no power sequencing requirements, that is, v dd(1v2) , v dd(emc) , v dd(io) , and v dda(3v3) can be switched on or off independent of each other. an internal circuit ensures that the system correctly powers up in the absence of core power. during io power-up this circuit takes care that the system is powered in a defined mode. the same is valid for core power-down. 10.3 power consumption per peripheral [1] all three ethernet clocks are in enabl ed in the mac_clk_ctrl register (see lpc32x0 user manual ). fig 4. minimum required core supply voltage for different core frequencies core frequency (mhz) 160 280 240 200 002aae872 1.0 1.2 1.4 0.8 vdd_core (v) table 9. power consumption per peripheral t amb =25 ? c; cpu clock = 208 mhz; i-cache/d-cac he, mmu disabled; vdd_core = 1.2 v; v dd(io) = 1.8 v; usb ahb, iram, and irom clocks a lways on; all peripherals are at their default state at reset. peripheral clocks are disabled except for peripheral measured. peripheral i dd(run) / ma high-speed uart (set to 115 200 bd (8n1)) 0.3 i 2 c-bus 0.3 ssp 0.6 i 2 s0 . 5 dma 6.3 emc 7.3 multi-level nand controller 1.4 single-level nand controller 0.3 lcd 5.6 ethernet mac [1] 2.9
lpc3220_30_40_50 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 2.1 ? 24 june 2014 54 of 80 nxp semiconductors lpc3220/30/40/50 16/32-bit arm microcontrollers 10.4 power consumpt ion in run mode power consumption is shown in figure 5 for wince applications running under typical conditions from sdram. mmu and i-cache/d-cache are enabled. the vfp is turned on but not used. i 2 s-interface (channel 1), lcd, slc nand controller, i 2 c1-bus, sd card, touchscreen adc, and uart 3 are turned on. all other peripherals are turned off. the ahb clock hclk is identical to the core clock for frequencies up to 133 mhz, which is the maximum allowed hclk frequency. for higher core frequencies, the hclk pll output must be divided by 2 to obtain an hc lk frequency lower than or equal to 133 mhz resulting in corresponding ly lower power consumptio n by the ahb peripherals. conditions: t amb =25 ? c; vdd_core = 1.2 v for core frequencies ? 208 mhz; vdd_core = 1.35 v for core frequencies > 208 mhz; v dd(io) = 1.8 v. (1) wince running from sdram; playing wmv file at 20 frames/s, 32 khz mono. (2) wince running from sdram; playing mp3 file at 128 kbit/s, stereo. (3) wince running from sdram; no application running. fig 5. core current versus core frequency for wince applications core frequency (mhz) 40 280 200 120 002aae762 80 40 120 160 i dd(run) (ma) 0 (1) (2) (3) hclk = 133 mhz hclk = 72 mhz vdd_core = 1.2 v vdd_core = 1.35 v
lpc3220_30_40_50 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 2.1 ? 24 june 2014 55 of 80 nxp semiconductors lpc3220/30/40/50 16/32-bit arm microcontrollers 10.5 adc static characteristics [1] conditions: v ssa = 0 v (on pin vss_ad); v dda(3v3) = 3.3 v (on pin vdd_ad). [2] the adc is monotonic; there are no missing codes. [3] the differential linearity error (e d ) is the difference between the actual step width and the ideal step width. see figure 6 . [4] the integral non-linearity (e l(adj) ) is the peak difference between the center of the st eps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset errors. see figure 6 . [5] the offset error (e o ) is the absolute difference between the straight line which fits the actual cu rve and the straight line which fits the ideal curve. see figure 6 . [6] the gain error (e g ) is the relative difference in percent between the straight line fitting the actual transfe r curve after removing offset error, and the straight line which fits the ideal transfer curve. see figure 6 . [7] the absolute error (e t ) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated adc and the ideal transfer curve. see figure 6 . table 10. adc static characteristics v dda(3v3) =3.3v; t amb =25 ? c unless otherwise specified; adc clock frequency 4.5 mhz. symbol parameter conditions min typ max unit v ia analog input voltage 0 - v dda(3v3) v c ia analog input capacitance - - 1 pf e d differential linearity error [1] [2] [3] - ? 0.5 ? 1lsb e l(adj) integral non-linearity [1] [4] - ? 0.6 ? 1lsb e o offset error [1] [5] - ? 1 ? 3lsb e g gain error [1] [6] - ? 0.3 ? 0.6 % e t absolute error [1] [7] - ? 4lsb r vsi voltage source interface resistance - - 40 k ?
lpc3220_30_40_50 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 2.1 ? 24 june 2014 56 of 80 nxp semiconductors lpc3220/30/40/50 16/32-bit arm microcontrollers (1) example of an actual transfer curve. (2) the ideal transfer curve. (3) differential linearity error (e d ). (4) integral non-linearity (e l(adj) ). (5) center of a step of the actual transfer curve. fig 6. adc characteristics 002aae434 1023 1022 1021 1020 1019 (2) (1) 1024 1018 1019 1020 1021 1022 1023 7 123456 7 6 5 4 3 2 1 0 1018 (5) (4) (3) 1 lsb (ideal) code out v dda(3v3) ? v ssa 1024 offset error e o gain error e g offset error e o v ia (lsb ideal ) 1 lsb =
lpc3220_30_40_50 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 2.1 ? 24 june 2014 57 of 80 nxp semiconductors lpc3220/30/40/50 16/32-bit arm microcontrollers 11. dynamic characteristics 11.1 clocking and i/o port pins [1] parameters are valid over operating tem perature range unless otherwise specified. [2] after supply voltages are stable [3] supplied by an external crystal. 11.2 static memory controller table 11. dynamic characteristics t amb = ? 40 ? c to +85 ? c, unless otherwise specified. [1] symbol parameter conditions min typ max unit reset t w(reset )ext external reset pulse width [2] 10 - - ms external clock f ext external clock frequency [3] 11 32 0m h z port pins t r rise time - 5 - ns t f fall time - 5 - ns table 12. dynamic characteristics: static external memory interface c l =25pf, t amb =20 ? c, v dd(emc) = 1.8 v, 2.5 v, or 3.3 v. symbol parameter notes min typ max unit common to read and write cycles t clcl clock cycle time [1] 7.5 9.6 - ns t cslav cs low to address valid time - 0 - ns read cycle parameters t oelav oe low to address valid time [2] -0 ? waitoen ? t clcl -ns t blslav bls low to address valid time [2] -0 ? waitoen ? t clcl -ns t csloel cs low to oe low time - 0 + waitoen ? t clcl -ns t cslblsl cs low to bls low time [2] - 0 + waitoen ? t clcl -ns t oeloeh oe low to oe high time [2] [3] -(waitrd ? waitoen + 1) ? t clcl -ns t blslblsh bls low to bls high time [2] [3] -(waitrd ? waitoen + 1) ? t clcl -ns t su(dq) data input/output set-up time [6] -8.4 - ns t h(dq) data input/output hold time [6] -0 - ns t cshoeh cs high to oe high time - 0 - ns t cshblsh cs high to bls high time - 0 - ns t oehanv oe high to address invalid time - 1 ? t clcl -ns t blshanv bls high to address invalid time - 1 ? t clcl -ns write cycle parameters t csldv cs low to data valid time - 0 - ns t cslwel cs low to we low time [4] -(waitwen+1) ? t clcl -ns t cslblsl cs low to bls low time [4] -(waitwen+ 1) ? t clcl -ns t weldv we low to data valid time [4] -0 ? (waitwen + 1) ? t clcl -ns
lpc3220_30_40_50 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 2.1 ? 24 june 2014 58 of 80 nxp semiconductors lpc3220/30/40/50 16/32-bit arm microcontrollers [1] t clcl = 1/hclk [2] refer to the lpc32x0 user manual emcstaticwaitoen0-3 register for the programming of waitoen value. [3] refer to the lpc32x0 user manual emcstaticwaitrd0-3 register for the programming of waitrd value. [4] refer to the lpc32x0 user manual emcstaticwaitwen0-3 register for the programming of waitwen value. [5] refer to the lpc32x0 user manual emcstaticwaitwr0-3 register for the programming of waitwr value. [6] earliest of cs high, oe high, address change to data invalid. t welweh we low to we high time [4] [5] -(waitwr ? waitwen + 1) ? t clcl -ns t blslblsh bls low to bls high time [4] [5] -(waitwr ? waitwen + 1) ? t clcl -ns t wehanv we high to address invalid time - 1 ? t clcl -ns t wehdnv we high to data invalid time - 1 ? t clcl -ns t blshanv bls high to address invalid time - 1 ? t clcl -ns t blshdnv bls high to data invalid time - 1 ? t clcl -ns table 12. dynamic characteristics: static external memory interface ?continued c l =25pf, t amb =20 ? c, v dd(emc) = 1.8 v, 2.5 v, or 3.3 v. symbol parameter notes min typ max unit fig 7. external memory read access emc_cs[3:0] emc_a[23:0] emc_d[31:0] emc_oe emc_bls[3:0] t cslav t oelav t oeloeh t csloel t su(dq) t h(dq) t cshoeh t oehanv 002aae402 t blslav t cshblsh t blslblsh t cslblsl t blshanv
lpc3220_30_40_50 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 2.1 ? 24 june 2014 59 of 80 nxp semiconductors lpc3220/30/40/50 16/32-bit arm microcontrollers fig 8. external memory write access emc_a[23:0] emc_d[31:0] t cslwel t cslblsl t weldv t csldv t welweh t wehanv t blshanv t wehdnv t blshdnv 002aae469 t cslav emc_cs[3:0] t blslblsh emc_bls[3:0] emc_wr
lpc3220_30_40_50 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 2.1 ? 24 june 2014 60 of 80 nxp semiconductors lpc3220/30/40/50 16/32-bit arm microcontrollers 11.3 sdr sdram controller [1] parameters are valid over operating tem perature range unless otherwise specified. [2] typical values valid for emc pads set to fast slew rate: vdd_emc = 1.8 v, vdd_core = 1.2 v or slower slew rate: vdd_emc = 3. 3 v, vdd_core = 1.2 v (see sdramclk_ctrl register in the lpc32x0 user manual ). [3] all min or max values valid for emc pads set to fast slew rate: vdd_emc = 1.8 v, vdd_core = 1.2 v or slower slew rate: vdd_em c = 3.3 v, vdd_core = 1.2 v. [4] f oper = 1/t ck. [5] applies to signals: emc_dqm[3:0], emc_dycs[1:0] , emc_ras , emc_cas , emc_wr , emc_cke[1:0]. [6] cmd_dly = command_delay bit field in sdramclk_ctrl[18:14] register, see external memory controller (emc) chapter in lpc32x0 user manual . table 13. emc sdr sdram memory in terface dynamic characteristics c l =25pf, t amb = ? 40 ? c to +85 ? c, unless otherwise specified. [1] [3] symbol parameter min typical [2] max unit f oper operating frequency [4] 104 133 mhz t ck clock cycle time 7.5 9.6 - ns t cl ck low-level width - 4.8 - ns t ch ck high-level width - 4.8 - ns t d(v)ctrl control valid delay time [5] [6] - (cmd_dly ? 0.25) + 2.7 ns t h(ctrl) control hold time [5] [6] (cmd_dly ? 0.25) + 1.2 - ns t d(av) address valid delay time [6] - (cmd_dly ? 0.25) + 3.2 ns t h(a) address hold time [6] (cmd_dly ? 0.25) + 1.2 - ns t d(qv) data output valid delay time [6] - (cmd_dly ? 0.25) + 3.5 ns t h(q) data output hold time [6] (cmd_dly ? 0.25) + 1.2 - ns t su(d) data input set-up time - 0.6 - ns t h(d) data input hold time - 0.9 - ns t qz data output high-impedance time - - ? t ck ns fig 9. sdr sdram signal timing 002aae420 emc_clk output signal (o) input signal (i) t d(v)ctrl , t d(av) , t d(qv) t h(ctrl) , t h(q) , t h(a) t h(d) t su(d) t ck t cl t ch t qz
lpc3220_30_40_50 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 2.1 ? 24 june 2014 61 of 80 nxp semiconductors lpc3220/30/40/50 16/32-bit arm microcontrollers 11.4 ddr sdram controller [1] all values valid for emc pads set to fast slew rate at 1. 8 v unless otherwise specified (see sdramclk_ctrl register in the lpc32x0 user manual ). [2] cmd_dly = command_delay bit field in sdramclk_ctrl[18:14] register, see external memory controller (emc) chapter in lpc32x0 user manual . [3] applies to signals emc_dqm[3:0], emc_dycs[1:0] , emc_ras , emc_cas , emc_wr , emc_cke[1:0]. [4] dqs_delay, see lpc32x0 user manual, external memory controll er chapter, section 8 ddr dqs delay calibration for details on configuring this value. [5] test conditions for measurements: t amb = ?40 ? c to +85 ? c; operating frequency range f oper = 52 mhz to 133 mhz; emc_dqm[3:0] and emc_d[31:0] driving 2 inches of 50 ? characteristic impedance trace with 10 pf capacitive load; no exte rnal source series termination resistors used. emc pads set to fast slew rate at 1.8 v or 2.5 v (see sdramclk_ctrl register in the lpc32x0 user manual ). table 14. emc ddr sdram memory interface dynamic characteristics [1] c l =25pf, t amb =25 ? c, unless otherwise specified. symbol parameter conditions min typical max unit f oper operating frequency - 104 133 mhz t ck clock cycle time 7.5 9.6 - ns t cl ck low-level width - 0.5 ? t ck -ns t ch ck high-level width - 0.5 ? t ck -ns t d(v)ctrl control valid delay time [2] [3] - (cmd_dly ? 0.25) + 1.5 - ns t h(ctrl) control hold time [2] [3] - (cmd_dly ? 0.25) ? 1.5 - ns t d(av) address valid delay time [2] - (cmd_dly ? 0.25) + 1.5 - ns t h(a) address hold time [2] - (cmd_dly ? 0.25) ? 1.5 - ns t su(q) data output set-up time emc_d[31:0] and emc_dqm[3:0] to emc_dqs[1:0] out [5] 0.08 ? t ck 0.15 ? t ck 0.25 ? t ck ns t h(q) data output hold time emc_d[31:0] and emc_dqm[3:0] to emc_dqs[1:0] out [5] 0.25 ? t ck 0.35 ? t ck 0.42 ? t ck ns t dqsh dqs high time for write command -0.5 ? t ck -ns t dqsl dqs low time for write command -0.5 ? t ck -ns t dqss write command to first dqs latching transition time for dqs out - t ck + 0.7 - ns t dss dqs falling edge to ck set-up time for dqs in - 0.5 ? t ck -ns t dsh dqs falling edge hold time from ck for dqs in - 0.5 ? t ck -ns t d(dqs) dqs delay time for dqs in [4] -dqs_delay -ns t su(d) data input set-up time - 0.3 - ns t h(d) data input hold time - 0.5 - ns
lpc3220_30_40_50 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 2.1 ? 24 june 2014 62 of 80 nxp semiconductors lpc3220/30/40/50 16/32-bit arm microcontrollers fig 10. ddr control timing parameters emc_clk emc control and address signals 002aae436 t ck t ch t cl t d(av); t d(v)ctrl t h(a); t h(ctl) valid fig 11. ddr write timing parameters command emc_d[31:0], emc_dqm[3:0] t dqsl t dqsh t dqss t h(q) emc_dqs[1:0] emc_clk 002aae437 write t su(q) t dsh t dss (1) the delay of the emc_dqs[1:0] signal is determined by the dqs_delay settings. see lpc32x0 user manual, external memory controller chapter, section ddr dqs delay calibration for details on configuring this value. fig 12. ddr read timing parameters emc_clk command emc_d[31:0] t su(d) emc_dqs[1:0] 002aae438 t h(d) read delayed emc_dqs[1:0] (1) t d(dqs)
lpc3220_30_40_50 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 2.1 ? 24 june 2014 63 of 80 nxp semiconductors lpc3220/30/40/50 16/32-bit arm microcontrollers 11.5 usb controller [1] parameters are valid over operating tem perature range unless otherwise specified. 11.6 secure digital (sd) card interface [1] parameters are valid over operating tem perature range unless otherwise specified. [2] typical ratings are not guaranteed. the va lues listed are at room temperature (25 ? c), nominal supply voltages. table 15. dynamic characteristics usb digital i/o pins v dd(io) = 3.3 v; t amb = ? 40 ? c to +85 ? c, unless otherwise specified. [1] symbol parameter conditions min typ max unit t tio bus turnaround time (i/o) oe_n/int_n to dat/vp and se0/vm - 7 - ns t toi bus turnaround time (o/i) oe_n/int_n to dat/vp and se0/vm - 0 - ns fig 13. usb bus turnaround time 002aae440 usb_dat_vp t tio t toi usb_oe_tp usb_se0_vm input output input table 16. dynamic characteristics: sd card pin interface t amb = ? 40 ? c to +85 ? c for industrial applications; v dd(io) over specified ranges. [1] symbol parameter conditions min typ [2] max unit t cy(clk) clock cycle time on pin ms_sclk; data transfer mode - - 25 mhz on pin ms_sclk; identification mode - - 400 khz t su(d) data input set-up time on pins ms_bs, ms_dio[3:0] as inputs - 2.7 - ns t h(d) data input hold time on pins ms_bs, ms_dio[3:0] as inputs - 0 - ns t d(qv) data output valid delay time on pins ms_bs, ms_dio[3:0] as outputs - 9.7 - ns t h(q) data output hold time on pins ms_bs, ms_dio[3:0] as outputs - 7.7 - ns
lpc3220_30_40_50 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 2.1 ? 24 june 2014 64 of 80 nxp semiconductors lpc3220/30/40/50 16/32-bit arm microcontrollers 11.7 mlc nand flash memory controller [1] t hclk = 1/hclk [2] cea d = bit field tcea_delay[1:0] in register mlc_time_reg[25:24] [3] w l = bit field wr_low[3:0] in register mlc_time_reg[3:0] [4] w h = bit field wr_high[3:0] in register mlc_time_reg[7:4] [5] r l = bit field rd_low[3:0] in register mlc_time_reg[11:8] [6] r h = bit field rd_high [3:0] in register mlc_time_reg[15:12] [7] r hz = bit field nand_ta[2:0] in register mlc_time_reg[18:16] [8] b d = bit field busy_delay[4:0] in register mlc_time_reg[23:19] fig 14. sd card pin interface timing 002aae441 ms_sclk ms_dio[3:0](o) ms_dio[3:0] (i) t d(qv) t h(d) t su(d) t cy(clk) t h(q) ms_bs (o) ms_bs (i) table 17. dynamic characteristics of the mlc nand flash memory controller t amb = ? 40 ? c to +85 ? c. symbol parameter min typ max unit t celrel ce low to re low time [1] [2] -t hclk ? cea d -ns t rc re cycle time [1] [5] [6] -t hclk ? (r l + 1) + t hclk ? (r h ? r l )- ns t reh re high hold time [1] [5] [6] -t hclk ? (r h ? r l )- n s t rhz re high to output high-impedance time [1] [5] [7] -t hclk ? (r h ? r l ) + t hclk ? r hz -ns t rp re pulse width [1] [5] -t hclk ? (r l + 1) - ns t rehrbl re high to r/b low time [1] [8] -t hclk ? b d -ns t wb we high to r/b low time [1] [8] -t hclk ? b d -ns t wc we cycle time [1] [3] [4] -t hclk ? (w l + 1) + t hclk ? (w h ? w l )- ns t wh we high hold time [1] [3] [4] -t hclk ? (w h ? w l )- n s t wp we pulse width [1] [3] -t hclk ? (w l + 1) - ns
lpc3220_30_40_50 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 2.1 ? 24 june 2014 65 of 80 nxp semiconductors lpc3220/30/40/50 16/32-bit arm microcontrollers 11.8 slc nand flash memory controller fig 15. mlc nand flash controller wr ite timing (writi ng to nand flash) fig 16. mlc nand flash controller read timing (reading from nand flash) t wb flash_io[7:0] flash_wr t wp t wc flash_rdy (r/b) flash_ce d0 d1 dn 10h t wh 002aae442 flash_io[7:0] t rp t reh t rc flash_rd flash_ce t celrel d0 d1 d2 d3 t rhz 002aae443 table 18. dynamic characteristics of slc nand flash memory controller t amb = ? 40 ? c to +85 ? c. symbol parameter conditions min typ max unit t als ale set-up time read [1] [2] [4] [6] -t hclk ? (rsu + rw) - ns write - t hclk ? (wsu + ww) - ns t alh ale hold time read [1] [7] -t hclk ? rh - ns write - t hclk ? wh - ns t ar ale to re delay time read [1] [2] [6] -t hclk ? rsu - ns write - t hclk ? wsu - ns
lpc3220_30_40_50 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 2.1 ? 24 june 2014 66 of 80 nxp semiconductors lpc3220/30/40/50 16/32-bit arm microcontrollers t cea ce access time read [1] [2] [4] [6] [8] -t hclk ? (rsu + rw) - ns write - t hclk ? (wsu + ww) - ns t cs ce set-up time read [1] [2] [4] [6] [8] -t hclk ? (rsu + rw) - ns write - t hclk ? (wsu + ww) - ns t ch ce hold time read [1] [3] -t hclk ? rh - ns write - t hclk ? wh - ns t cls cle set-up time read [1] [2] [4] [6] [8] -t hclk ? (rsu + rw) - ns write - t hclk ? (wsu + ww) - ns t clh cle hold time read [1] [3] -t hclk ? rh - ns write - t hclk ? wh - ns t clr cle to re delay time read [1] [2] [6] -t hclk ? rsu - ns write - t hclk ? wsu - ns t dh data hold time output from nand controller; read [1] [3] [7] -t hclk ? rh - ns output from nand controller; write -t hclk ? wh - ns t ds data set-up time output from nand controller; read [1] [2] [4] [6] [8] -t hclk ? (rsu + rw) - ns output from nand controller; write -t hclk ? (wsu + ww) - t ir output high-impedance to re low time read [1] [2] [6] -t hclk ? rsu - ns write - t hclk ? wsu - ns t rc re cycle time read [1] [2] -t hclk ? (rsu + rw + rh) - ns t rea re access time read [1] [4] -t hclk ? rw - ns t reh re high hold time read [1] [2] [3] -t hclk ? (rsu + rh) - ns t rhoh re high to output hold time input hold for flash controller; read -0 -- input hold for flash controller; write -0 -- t rhz re high to output high-impedance time read [1] -t hclk ? rh - ns t rp re pulse width read [1] [4] -t hclk ? rw - ns t rr ready to re low time read [1] [2] [3] -t hclk ? rsu - ns t wb we high to r/b low time write [1] [7] [9] -(t hclk ? wh) + (2 ? t hclk ? wb) -ns t wc we cycle time write [1] [6] [7] [8] -t hclk ? (wsu + ww + wh) - ns table 18. dynamic characteristics of slc nand flash memory controller ?continued t amb = ? 40 ? c to +85 ? c. symbol parameter conditions min typ max unit
lpc3220_30_40_50 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 2.1 ? 24 june 2014 67 of 80 nxp semiconductors lpc3220/30/40/50 16/32-bit arm microcontrollers [1] t hclk = 1/hclk [2] rsu = bit field r_setup[3:0] in register slc_tac[3:0] for reads [3] rh = bit field r_hold[3:0] in register slc_tac[7:4] for reads [4] rw = bit field r_width[3:0] in register slc_tac[11:8] for reads [5] rb = bit field r_rdy[3:0] in register slc_tac[15:12] for reads [6] wsu = bit field w_setup[3:0] in register slc_tac[19:16] for writes [7] wh = bit field w_hold[3:0] in register slc_tac[23:20] for writes [8] ww = bit field w_width[3:0] in register slc_tac[27:24] for writes [9] wb = bit field w_rdy[3:0] in register slc_tac[31:28] for writes t wh we high hold time write [1] [6] [7] -t hclk ? (wsu + wh) - ns t whr we high to re low time write [1] [7] [9] -(t hclk ? wh) + (2 ? t hclk ? wb) -ns t wp we pulse width write [1] [8] -t hclk ? ww - ns t rehrbl re high to r/b low time write [1] [3] [5] -(t hclk ? rh) + (2 ? t hclk ? rb) -ns table 18. dynamic characteristics of slc nand flash memory controller ?continued t amb = ? 40 ? c to +85 ? c. symbol parameter conditions min typ max unit fig 17. mlc nand flash memory writ e timing (writing to nand flash) command t ds t dh t wb flash_io[7:0] address t ds t dh t als t alh t ds t dh t wp t wh t wc t cs t ch t ch t cls t clh command address data d0 d1 dn t als t clh t als t alh t wp t wp t wh t cls t cs 002aae444 flash_ce flash_cle flash_wr flash_ale flash_rdy
lpc3220_30_40_50 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 2.1 ? 24 june 2014 68 of 80 nxp semiconductors lpc3220/30/40/50 16/32-bit arm microcontrollers fig 18. mlc nand flash memory read timing (reading from nand flash) command t ds t dh t wb flash_io[7:0] address t ds t dh t als t alh t ds t dh t rp t reh t rc t rr t ar t cs t ch t cea t clr t cls t clh command address data t coh t rea d0 d1 d2 d3 t rhz t rhoh t als t alh t cls t cs t wp t wh t wp 002aae445 flash_ale flash_cle flash_rdy flash_wr flash_rd flash_ce
lpc3220_30_40_50 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 2.1 ? 24 june 2014 69 of 80 nxp semiconductors lpc3220/30/40/50 16/32-bit arm microcontrollers 11.9 spi and ssp controller 11.9.1 spi [1] t hclk = period time of spi ip block input clock (hclk) fig 19. mlc nand flash memory status timing t cs t ch t cea 70 h t ds t dh status t rhoh t cls t clh command data t clr t coh t rea t ir flash_io[7:0] t whr t wp t rhz flash_cle flash_wr flash_ce flash_rd 002aae446 table 19. dynamic characteristics of spi pins on spi master controller t amb = ? 40 ? c to +85 ? c. symbol parameter min typ max unit common to spi1 and spi2 t spicyc spi cycle time [1] 2 ? t hclk - 256 ? t hclk ns spi1 t spidsu spi data set-up time - 6 - ns t spidh spi data hold time - 0 - ns t spidv spi enable to output data valid time - 2 - ns t spioh spi output data hold time - 0 - ns spi2 t spidsu spi data set-up time - 10 - ns t spidh spi data hold time - 0 - ns t spidv spi enable to output data valid time - 2 - ns t spioh spi output data hold time - 0 - ns
lpc3220_30_40_50 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 2.1 ? 24 june 2014 70 of 80 nxp semiconductors lpc3220/30/40/50 16/32-bit arm microcontrollers 11.9.2 timing diagrams for spi and ssp (in spi mode) fig 20. spi master timing (cpha = 0) fig 21. spi master timing (cpha = 1) 002aae457 t spicyc t spiclkh t spiclkl t spidsu t spidh data valid data valid t spioh data valid data valid t spiqv spi1/2_clk or sck0/1 (cpol = 0) spi1/2_clk or sck0/1 (cpol = 1) spi1/2_dataio or mosi0/1 spi1/2_datain or miso0/1 002aae454 t spicyc t spiclkh t spiclkl t spidsu t spidh t spiqv data valid data valid t spioh data valid data valid spi1/2_clk or sck0/1 (cpol = 0) spi1/2_clk or sck0/1 (cpol = 1) spi1/2_dataio or mosi0/1 spi1/2_datain or miso0/1
lpc3220_30_40_50 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 2.1 ? 24 june 2014 71 of 80 nxp semiconductors lpc3220/30/40/50 16/32-bit arm microcontrollers 12. application information 12.1 connecting the jtag_ntrst pin to ensure that pin jtag_ntrst is low at por, use one the following board design options: ? tie jtag_ntrst low. in this case, you will not be able to use the jtag port in a production design. tying jtag_ntrst low does not affect normal operation (code execution) of the part but does prevent jtag access. ? implement recommended circuit shown in figure 24 . fig 22. spi slave timing (cpha = 0) fig 23. spi slave timing (cpha = 1) 002aae458 t spicyc t spiclkh t spiclkl t spidsu t spidh t spiqv data valid data valid t spioh data valid data valid spi1/2_clk or sck0/1 (cpol = 0) spi1/2_clk or sck0/1 (cpol = 1) spi1/2_dataio or mosi0/1 spi1/2_datain or miso0/1 002aae459 t spicyc t spiclkh t spiclkl t spidsu t spidh t spiqv data valid data valid t spioh data valid data valid spi1/2_clk or sck0/1 (cpol = 0) spi1/2_clk or sck0/1 (cpol = 1) spi1/2_dataio or mosi0/1 spi1/2_datain or miso0/1
lpc3220_30_40_50 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 2.1 ? 24 june 2014 72 of 80 nxp semiconductors lpc3220/30/40/50 16/32-bit arm microcontrollers fig 24. circuit for holding jtag_ntrst low during por aaa-013571 jtag_ntrst lpc32x0 jtag_tdi jtag_tms jtag_tck jtag_rtck jtag_tdo reset jtag_ntrst jtag_tdi jtag_tms jtag_tck jtag_rtck jtag_tdo jtag_ntrst hdr-1x02 vdd_iod +3.3 v jtag_tdi jtag_tms jtag_tck jtag_rtck jtag_tdo jtag_nsrst jtag_dbgrq jtag_dbgack jtag_nsrst 1 3 bat54c.215 lpc_nreset 10 k 10 k 10 k 10 k 10 k 10 k 100 k 10 k 10 k 10 k 10 k 33 vdd_rtc 6 4 1y 2y 1a 1 3 2 5 7 9 11 13 15 17 19 2a 2 1 3 nreset pwr-on-reset gnd jtag connector vcc +3.3 v 1 3 gnd 74lvc2g07w d2520-6002-ar apx809-26sa vcc 2 5 vdd_iod board_reset 4 6 8 10 12 14 16 18 20
lpc3220_30_40_50 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 2.1 ? 24 june 2014 73 of 80 nxp semiconductors lpc3220/30/40/50 16/32-bit arm microcontrollers 13. package outline fig 25. package outline sot1048-1 (tfbga296) references outline version european projection issue date iec jedec jeita sot1048-1 mo-216 sot1048-1 07-10-19 07-11-02 unit a max mm 1.2 0.4 0.3 0.80 0.65 15.1 14.9 15.1 14.9 0.8 13.6 0.15 0.08 0.1 a 1 dimensions (mm are the original dimensions) tfbga296: plastic thin fine-pitch ball grid array package; 296 balls 0 5 10 mm scale a 2 b 0.5 0.4 d e e e 1 e 2 13.6 v w y 0.12 y 1 c y c y 1 x a b c d e f h k g l j m n p r t u 246810121416 13579111315 18 17 b e 2 e 1 e e 1/2 e 1/2 e ac b ? v m c ? w m ball a1 index area v b a ball a1 index area d e detail x a a 2 a 1
lpc3220_30_40_50 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 2.1 ? 24 june 2014 74 of 80 nxp semiconductors lpc3220/30/40/50 16/32-bit arm microcontrollers 14. abbreviations table 20. abbreviations acronym description adc analog-to-digital converter ahb advanced high-performance bus amba advanced microcontroller bus architecture apb advanced peripheral bus bsdl boundary scan description language cisc complex instruction set computer ddr sdram double data rate synchronous dynamic random access memory dma direct memory access dsp digital signal processing etm embedded trace macrocell fab fast access bus fifo first in, first out fiq fast interrupt request gpio general purpose input/output i/o input/output irq interrupt request hs high-speed irda infrared data association jtag joint test action group lcd liquid crystal display mac media access control miim media independent interface management ohci open host controller interface otg on-the-go phy physical layer pll phase-locked loop pwm pulse width modulator ram random access memory rmii reduced media independent interface se0 single ended zero sdr sdram single data rate synchronous dynamic random access memory spi serial peripheral interface ssi serial synchronous interface ssp synchronous serial port tft thin film transistor ttl transistor-transistor logic stn super twisted nematic
lpc3220_30_40_50 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 2.1 ? 24 june 2014 75 of 80 nxp semiconductors lpc3220/30/40/50 16/32-bit arm microcontrollers 15. references [1] lpc3220/30/40/50 user manual um10326: http://www.nxp.com/documen ts/user_manual/um10326.pdf [2] lpc3220/30/40/50 errata sheet: http://www.nxp.com/documents/errata_sheet/es_lpc3250.pdf uart universal asynchronous receiver/transmitter usb universal serial bus vfp vector floating point processor table 20. abbreviations ?continued acronym description
lpc3220_30_40_50 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 2.1 ? 24 june 2014 76 of 80 nxp semiconductors lpc3220/30/40/50 16/32-bit arm microcontrollers 16. revision history table 21. revision history document id release date data sheet status change notice supersedes lpc3220_30_40_50 v.2.1 20140624 product data sheet cin 201110012i lpc3220_30_40_50 v.2 modifications: section 12.1 ? connecting the jtag_ntrst pin ? added. lpc3220_30_40_50 v.2 20111020 product data sheet - lpc3220_30_40_50 v.1 modifications: ? corrected pin functions for pin t14 (adi n1/ts_xm) and pin u15 (adin0/ts_ym) in table 3 and table 4. ? power domain for pin pll397_loop corrected in table 4. ? power supply domain for pins sysx_in and sysx_out pins corrected in table 4. ? power supply domain for pin vdd_osc corrected in table 4. ? description of debug pin updated in table 4. ? added table 6 ?supply domains?. ? changed v esd to 2500 v (hbm) and 1000 v (cdm) in table 7. ? power consumption for hclk, usb, and adc added in table 8. ? parameter i dd(rtc) updated in table 8. ? parameter v dd(emc) table notes updated in table 8. ? input current for bus keeper inputs added in table 8. ? added power consumption data (table 8, table 9, and figure 5). ? static memory controller: added t su(dq) value in table 12. ? ddr sdram controller: updated t dqss value in table 14. ? minimum and maximum characterization data added for parameters t su(q) and t h(q) over temperature range ? 40 ? c to +85 ? c (see table 14). ? ddr sdram characteristics extended to maximum operating frequency f oper = 133 mhz (see table 14). ? parameters t wb , t whr , and t rehrbl updated in table 18. ? changed data sheet status to product data sheet. ? parts lpc3220fet296/01, lpc323 0fet296/01, lpc3240fet296/01, lpc3250fet296/01 added. lpc3220_30_40_50 v.1 20090206 preliminary data sheet - -
lpc3220_30_40_50 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 2.1 ? 24 june 2014 77 of 80 nxp semiconductors lpc3220/30/40/50 16/32-bit arm microcontrollers 17. legal information 17.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 17.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 17.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such info rmation. nxp semiconductors takes no responsibility for the content in this document if provided by an information source outside of nxp semiconductors. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors and its suppliers accept no liability for inclusion and/or use of nxp semiconducto rs products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this document contains the product specification.
lpc3220_30_40_50 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 2.1 ? 24 june 2014 78 of 80 nxp semiconductors lpc3220/30/40/50 16/32-bit arm microcontrollers export control ? this document as well as the item(s) described herein may be subject to export control regu lations. export might require a prior authorization from competent authorities. non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semicon ductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liabili ty for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without nxp semiconductors? warranty of the product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully indemnifies nxp semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive app lications beyond nxp semiconductors? standard warranty and nxp semiconduct ors? product specifications. 17.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. i 2 c-bus ? logo is a trademark of nxp semiconductors n.v. 18. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
lpc3220_30_40_50 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 2.1 ? 24 june 2014 79 of 80 continued >> nxp semiconductors lpc3220/30/40/50 16/32-bit arm microcontrollers 19. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 ordering information . . . . . . . . . . . . . . . . . . . . . 4 4.1 ordering options . . . . . . . . . . . . . . . . . . . . . . . . 4 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 6 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . 10 7 functional description . . . . . . . . . . . . . . . . . . 24 7.1 cpu and subsystems . . . . . . . . . . . . . . . . . . . 24 7.1.1 cpu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.1.2 vector floating point (vfp) coprocessor . . . . 24 7.1.3 emulation and debugging . . . . . . . . . . . . . . . . 24 7.1.3.1 embedded ice . . . . . . . . . . . . . . . . . . . . . . . . 24 7.1.3.2 embedded trace buffer . . . . . . . . . . . . . . . . . . 25 7.2 ahb matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.2.1 apb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.2.2 fab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.3 physical memory map . . . . . . . . . . . . . . . . . . 26 7.4 internal memory . . . . . . . . . . . . . . . . . . . . . . . 28 7.4.1 on-chip rom . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.4.2 on-chip sram . . . . . . . . . . . . . . . . . . . . . . . . 28 7.5 external memory interfaces . . . . . . . . . . . . . . 28 7.5.1 nand flash controllers . . . . . . . . . . . . . . . . . . 28 7.5.1.1 multi-level cell (mlc) nand flash controller. 28 7.5.1.2 single-level cell (slc) nand flash controller 29 7.5.2 sd card controller . . . . . . . . . . . . . . . . . . . . . . 29 7.5.2.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.5.3 external memory controller. . . . . . . . . . . . . . . 29 7.6 ahb master peripherals . . . . . . . . . . . . . . . . . 30 7.6.1 general purpose dma (gpdma) controller . 30 7.6.2 ethernet mac . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.6.2.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.6.3 usb interface . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.6.3.1 usb device controller . . . . . . . . . . . . . . . . . . . 31 7.6.3.2 usb host controller. . . . . . . . . . . . . . . . . . . . . 32 7.6.3.3 usb otg controller . . . . . . . . . . . . . . . . . . . . 32 7.6.4 lcd controller. . . . . . . . . . . . . . . . . . . . . . . . . 33 7.6.4.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.7 system functions . . . . . . . . . . . . . . . . . . . . . . 34 7.7.1 interrupt controller . . . . . . . . . . . . . . . . . . . . . 34 7.7.2 watchdog timer. . . . . . . . . . . . . . . . . . . . . . . . 34 7.7.2.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.7.3 millisecond timer . . . . . . . . . . . . . . . . . . . . . . . 34 7.7.3.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.7.4 clocking and power control features . . . . . . . 35 7.7.4.1 clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.7.4.2 crystal oscillator. . . . . . . . . . . . . . . . . . . . . . . 35 7.7.4.3 plls. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.7.4.4 power control modes . . . . . . . . . . . . . . . . . . . 36 7.7.4.5 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.8 communication peripheral interfaces . . . . . . 36 7.8.1 uarts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.8.1.1 standard uarts. . . . . . . . . . . . . . . . . . . . . . . 37 7.8.1.2 high-speed uarts . . . . . . . . . . . . . . . . . . . . 37 7.8.2 spi serial i/o controller . . . . . . . . . . . . . . . . . 37 7.8.2.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.8.3 ssp serial i/o controller. . . . . . . . . . . . . . . . . 38 7.8.3.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.8.4 i 2 c-bus serial i/o controller . . . . . . . . . . . . . . 38 7.8.4.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.8.5 i 2 s-bus audio controller . . . . . . . . . . . . . . . . . 39 7.8.5.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.9 other peripherals . . . . . . . . . . . . . . . . . . . . . . 40 7.9.1 general purpose parallel i/ o . . . . . . . . . . . . . 40 7.9.1.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7.9.2 keyboard scanner . . . . . . . . . . . . . . . . . . . . . 41 7.9.2.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.9.3 touch screen controller and 10-bit adc . . . . 41 7.9.3.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.9.4 real-time clock (rtc) and battery ram . . . 41 7.9.4.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.9.5 enhanced 32-bit timers/external event counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.9.5.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.9.6 high-speed timer . . . . . . . . . . . . . . . . . . . . . . 43 7.9.6.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7.9.7 pulse width modulators (pwms) . . . . . . . . . . 43 7.9.7.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7.9.8 motor control pulse width modulator . . . . . . . 43 7.9.8.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8 basic architecture . . . . . . . . . . . . . . . . . . . . . . 44 9 limiting values . . . . . . . . . . . . . . . . . . . . . . . . 45 10 static characteristics . . . . . . . . . . . . . . . . . . . 46 10.1 minimum core voltage requirements . . . . . . . 53 10.2 power supply sequencing . . . . . . . . . . . . . . . 53 10.3 power consumption per pe ripheral . . . . . . . . 53 10.4 power consumption in run mode . . . . . . . . . 54 10.5 adc static characteristics . . . . . . . . . . . . . . . 55 11 dynamic characteristics. . . . . . . . . . . . . . . . . 57 11.1 clocking and i/o port pins . . . . . . . . . . . . . . . 57 11.2 static memory controller . . . . . . . . . . . . . . . . 57 11.3 sdr sdram controller. . . . . . . . . . . . . . . . . 60
nxp semiconductors lpc3220/30/40/50 16/32-bit arm microcontrollers ? nxp semiconductors n.v. 2014. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 24 june 2014 document identifier: lpc3220_30_40_50 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 11.4 ddr sdram controller . . . . . . . . . . . . . . . . . 61 11.5 usb controller . . . . . . . . . . . . . . . . . . . . . . . . 63 11.6 secure digital (sd) card interface . . . . . . . . . 63 11.7 mlc nand flash memory controller. . . . . . . . 64 11.8 slc nand flash memory controller . . . . . . . . 65 11.9 spi and ssp controller . . . . . . . . . . . . . . . . . 69 11.9.1 spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 11.9.2 timing diagrams for spi and ssp (in spi mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 12 application information. . . . . . . . . . . . . . . . . . 71 12.1 connecting the jtag_ntrst pin . . . . . . . . . 71 13 package outline . . . . . . . . . . . . . . . . . . . . . . . . 73 14 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 74 15 references . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 16 revision history . . . . . . . . . . . . . . . . . . . . . . . . 76 17 legal information. . . . . . . . . . . . . . . . . . . . . . . 77 17.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 77 17.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 17.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 17.4 trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 78 18 contact information. . . . . . . . . . . . . . . . . . . . . 78 19 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

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